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ZL40224LDG1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
VDD
VDD_Rx
Z
o
= 50 Ohms
Z
o
= 50 Ohms
ZL40224
clk_p
clk_n
100 nF
100 nF
R
CML
Receiver
50
Ohm
50
Ohm
R
VDD= 3.3V: R = 120 Ohm
VDD = 2.5 V: R = 60 Ohm
Figure 18 - LVPECL AC Output Termination for CML Inputs
ZL40224 Data Sheet
15
Microsemi Corporation
ZL40224 Data Sheet
16
Microsemi Corporation
3.3 Device Additive Jitter
The ZL40224 clock fan out buffer is not intended to filter clock jitter. The jitter performance of this type of device is
characterized by its additive jitter. Additive jitter is the jitter the device would add to a hypothetical jitter-free clock as
it passes through the device. The additive jitter of the ZL40224 is random and as such it is not correlated to the jitter
of the input clock signal.
The square of the resultant random RMS jitter at the output
of the ZL40224 is equal to the sum of the squares of the
various random RMS jitter sources including: input clock jitter; additive jitter of the buffer; and additive jitter due to
power supply noise. There may be additional deterministic jitter sources that are not shown in Figure 19.
+
J
in
2
J
out
2
= J
in
2
+J
add
2
+J
ps
2
J
add
2
J
ps
2
J
in
= Random input clock jitter (RMS)
J
add
= Additive jitter due to the device (RMS)
J
ps
= Additive jitter due to power supply noise (RMS)
J
out
= Resultant random output clock jitter (RMS)
+
Figure 19 - Additive Jitter
ZL40224 Data Sheet
17
Microsemi Corporation
3.4 Power Supply
This device operates with either a 2.5V supply or 3.3V supply.
3.4.1 Sensitivity to power supply noise
Power supply noise from sources such as switching power supplies and high-power digital components such as
FPGAs can induce additive jitter on clock buffer outputs. The ZL40224 is equipped with a low drop out (LDO) linear
power regulator and on-chip bulk capacitors to minimize additive jitter due to power supply noise. The on-chip
regulation, recommended power supply filtering, and good PCB layout all work together to minimize the additive
jitter from power supply noise.
3.4.2 Power supply filtering
For optimal jitter performance, the ZL40224 should be isolated from the power planes connected to its power
supply pins as shown in Figure 20.
• 10 µF capacitors should be size 0603 or size 080
5 X5R or X7R ceramic, 6.3 V minimum rating
• 0.1 µF capacitors should be
size 0402 X5R ceramic, 6.3 V minimum rating
• Capacitors should be placed next to the
connected device power pins
Figure 20 - Decoupling Connections for Power Pins
VDD
0.15 Ohms
10 µF
0.1 µF
0.1 µF
10 µF
ZL40224
9
19
22
32
3.4.3 PCB layout considerations
The power supply filtering shown in Figure 20 can be implemented either as a plane island, or as a routed power
topology with equal results.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27

ZL40224LDG1

Mfr. #:
Buy ZL40224LDG1
Manufacturer:
Microchip / Microsemi
Description:
Clock Buffer 2:8 LVPECL Fanout Buffer w/Ext. Term.
Lifecycle:
New from this manufacturer.
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