AD8565/AD8566/AD8567
Rev. G | Page 10 of 16
This input current is not inherently damaging to the device as
long as it is limited to 5 mA or less. If a condition exists using
the AD8565/AD8566/AD8567 where the input exceeds the
supply more than 0.6 V, an external series resistor should be
added. The size of the resistor can be calculated by using the
maximum over-voltage divided by 5 mA. This resistance should
be placed in series with either input exposed to an overvoltage.
OUTPUT PHASE REVERSAL
The AD8565/AD8566/AD8567 are immune to phase reversal.
Although device output does not change phase, large currents
due to input overvoltage could damage the device. In applica-
tions where the possibility of an input voltage exceeding the
supply voltage exists, overvoltage protection should be used as
described in the Input Overvoltage Protection section.
POWER DISSIPATION
The maximum allowable internal junction temperature of
150°C limits the maximum power dissipation of AD8565/
AD8566/AD8567 devices. As the ambient temperature
increases, the maximum power dissipated by AD8565/AD8566/
AD8567 devices must decrease linearly to maintain maximum
junction temperature. If this maximum junction temperature is
exceeded momentarily, the device still operates properly once
the junction temperature is reduced below 150°C. If the
maximum junction temperature is exceeded for an extended
period, overheating could lead to permanent damage of the
device.
The maximum safe junction temperature, T
JMAX
, is 150°C. Using
the following formula, the maximum power that an AD8565/
AD8566/AD8567 device can safely dissipate as a function of
temperature can be obtained:
P
DISS
= T
JMAX
T
A
JA
where:
P
DISS
is the AD8565/AD8566/AD8567 power dissipation.
T
JMAX
is the AD8565/AD8566/AD8567 maximum allowable
junction temperature (150°C).
T
A
is the ambient temperature of the circuit.
θ
JA
is the AD8565/AD8566/AD8567 package thermal resistance,
junction-to-ambient.
The power dissipated by the device can be calculated as
P
DISS
= (V
S
V
OUT
) × I
LOAD
where:
V
S
is the supply voltage.
V
OUT
is the output voltage.
I
LOAD
is the output load current.
Figure 30 shows the maximum power dissipation vs. temper-
ature. To achieve proper operation, use the previous equation to
calculate P
DISS
for a specific package at any given temperature or
use Figure 30.
AMBIENT TEMPERATURE (°C)
1.25
0.75
0
–35
MAXIMUM POWER DISSIPATION (W)
0.50
0.25
1.00
–15 5 25 45 65 85
16-LEAD LFCSP
5-LEAD SC70
8-L
EAD MSOP
14-LEAD TSSOP
01909-030
Figure 30. Maximum Power Dissipation vs. Temperature for 5-Lead SC70,
8-Lead MSOP, 14-Lead TSSOP, and 16-Lead LFCSP Packages
THERMAL PAD—AD8567
The AD8567 LFCSP comes with a thermal pad that is attached
to the substrate. This substrate is connected to the most positive
supply, that is, Pin 3 in the LFCSP package and Pin 4 in the
TSSOP package. To be electrically safe, the thermal pad should
be soldered to an area on the board that is electrically isolated
or connected to V
DD
. Attaching the thermal pad to ground
adversely affects the performance of the part.
Soldering down this thermal pad dramatically improves the
heat dissipation of the package. It is necessary to attach vias that
connect the soldered thermal pad to another layer on the board.
This provides an avenue to dissipate the heat away from the
part. Without vias, the heat is isolated directly under the part.
AD8565/AD8566/AD8567
Rev. G | Page 11 of 16
TOTAL HARMONIC DISTORTION + NOISE (THD + N)
The AD8565/AD8566/AD8567 feature low total harmonic dis-
tortion. Figure 31 shows THD + N vs. frequency. The THD + N
over the entire supply range is below 0.008%. When the device
is powered from a 16 V supply, the THD + N stays below
0.003%. Figure 31 shows the AD8566 in a unity noninverting
configuration.
FREQUENCY (Hz)
20
THD+N (%)
100
10
1
0.01
0.1
1k 10k 30k
V
S
= ±2.5V
V
S
= ±8V
01909-031
Figure 31. THD + N vs. Frequency
SHORT-CIRCUIT OUTPUT CONDITIONS
The AD8565/AD8566/AD8567 do not have internal short-
circuit protection circuitry. As a precautionary measure, it is
recommended not to short the output directly to the positive
power supply or to ground.
It is not recommended to operate the AD8565/AD8566/AD8567
with more than 35 mA of continuous output current. The
output current can be limited by placing a series resistor at the
output of the amplifier whose value can be derived using
mA35
S
X
V
R
For a 5 V single-supply operation, R
X
should have a minimum
value of 143 Ω.
LCD PANEL APPLICATIONS
The AD8565/AD8566/AD8567 amplifier is designed for LCD
panel applications or applications where large capacitive load
drive is required. It can instantaneously source/sink greater than
250 mA of current. At unity gain, it can drive 1 µF without
compensation. This makes the AD8565/AD8566/AD8567 ideal
for LCD V
COM
driver applications.
To evaluate the performance of the AD8565/AD8566/AD8567,
a test circuit was developed to simulate the V
COM
driver
application for an LCD panel. Figure 32 shows the test circuit.
Series capacitors and resistors connected to the output of the op
amp represent the load of the LCD panel. The 300 a n d 3 k
feedback resistors are used to improve settling time. This test
circuit simulates the worst-case scenario for a V
COM
. It drives a
represented load that is connected to a signal switched symmet-
rically around V
COM
.
Figure 33 shows a scope photo of the instantaneous output peak
current capability of the AD8565/AD8566/AD8567.
INPUT 0VTO 8V
SQUARE WAVE WITH
15.6µs PULSE WIDTH
300
3k
10 10 10 10
10nF
10nF 10nF 10nF
MEASURE
CURRENT
4V
8V
10TO 20
01909-032
Figure 32. V
COM
Test Circuit with Supply Voltage at 16 V
TIME (2µs/DIV)
01909-033
CH 2 = 100mA/DIV
CH 1 = 5V/DIV
10
0%
100
90
Figure 33. Scope Photo of the V
COM
Instantaneous Peak Current
AD8565/AD8566/AD8567
Rev. G | Page 12 of 16
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-AA
100709-B
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
Figure 34. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-203-AA
1.00
0.90
0.70
0.46
0.36
0.26
2.20
2.00
1.80
2.40
2.10
1.80
1.35
1.25
1.15
072809-A
0.10 MAX
1.10
0.80
0.40
0.10
0.22
0.08
3
1 2
45
0.65 BSC
COPLANARITY
0.10
SEATING
PLANE
0.30
0.15
Figure 35. 5-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-5)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
061908-A
4.50
4.40
4.30
14
8
7
1
6.40
BSC
PIN 1
5.10
5.00
4.90
0.65 BSC
0.15
0.05
0.30
0.19
1.20
MAX
1.05
1.00
0.80
0.20
0.09
0.75
0.60
0.45
COPLANARITY
0.10
SEATING
PLANE
Figure 36. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters

AD8565AKSZ-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Operational Amplifiers - Op Amps 16V RR SGL
Lifecycle:
New from this manufacturer.
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