AD9945
–3–
Parameter Min Typ Max Unit Notes
CDS
Maximum Input Range before Saturation* 1.0 Vp-p
Allowable CCD Reset Transient* 500 mV See Input Waveform in Footnote
Maximum CCD Black Pixel Amplitude* 100 mV
VARIABLE GAIN AMPLIFIER (VGA)
Gain Control Resolution 1024 Steps
Gain Monotonicity Guaranteed
Gain Range
Minimum Gain 5.3 dB
Maximum Gain 40.0 41.5 dB
BLACK LEVEL CLAMP
Clamp Level Resolution 256 Steps
Clamp Level Measured at ADC Output
Minimum Clamp Level 0 LSB
Maximum Clamp Level 255 LSB
A/D CONVERTER
Resolution 12 Bits
Differential Nonlinearity (DNL) ± 0.5 LSB
No Missing Codes Guaranteed
Data Output Coding Straight Binary
Full-Scale Input Voltage 2.0 V
VOLTAGE REFERENCE
Reference Top Voltage (REFT) 2.0 V
Reference Bottom Voltage (REFB) 1.0 V
SYSTEM PERFORMANCE Specifications Include Entire Signal Chain
Gain Range
Low Gain (VGA Code = 0) 5.3 dB
Maximum Gain (VGA Code = 1023) 40.0 41.5 dB
Gain Accuracy 1.0 dB
Peak Nonlinearity, 500 mV Input Signal 0.1 % 12 dB Gain Applied
Total Output Noise 1.2 LSB rms AC Grounded Input, 6 dB Gain Applied
Power Supply Rejection (PSR) 40 dB
*Input Signal Characteristics defined as follows:
500mV TYP
RESET TRANSIENT
100mV TYP
OPTICAL BLACK PIXEL
1V TYP
INPUT SIGNAL RANGE
Specifications subject to change without notice.
SYSTEM SPECIFICATIONS
REV.
C
, AVDD = DVDD = DRVDD = 3.0 V, f = 40 MHz, Register 0xD = 0x838,
unless otherwise noted.)
MAXMIN
(T to T
SAMP
See Variable Gain Amplifier section for VGA gain equation
Low Gain Mode
¦1.5 0 +1.5
dB
See Table 1, Internal Register Map, for register information
See Figure 7 for VGA Gain Curve
–4–
AD9945
TIMING SPECIFICATIONS
Parameter Symbol Min Typ Max Unit
SAMPLE CLOCKS
DATACLK, SHP, SHD Clock Period t
CONV
25 ns
DATACLK High/Low Pulse Width t
ADC
10 12.5 ns
SHP Pulse Width t
SHP
6.25 ns
SHD Pulse Width t
SHD
6.25 ns
CLPOB Pulse Width* t
COB
2 20 Pixels
SHP Rising Edge to SHD Falling Edge t
S1
6.25 ns
SHP Rising Edge to SHD Rising Edge t
S2
11.25 12.5 ns
Internal Clock Delay t
ID
3ns
DATA OUTPUTS
Output Delay t
OD
9.5 ns
Pipeline Delay 10 Cycles
SERIAL INTERFACE
Maximum SCK Frequency f
SCLK
10 MHz
SL to SCK Setup Time t
LS
10 ns
SCK to SL Hold Time t
LH
10 ns
SDATA Valid to SCK Rising Edge Setup t
DS
10 ns
SCK Falling Edge to SDATA Valid Hold t
DH
10 ns
*Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Specifications subject to change without notice.
(C
L
= 20 pF, f
SAMP
= 40 MHz, CCD Mode Timing in Figures 8 and 9, Serial Timing in Figures 4 and 5.)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9945 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*
With
Respect
Parameter To Min Max Unit
AVDD AVSS –0.3 +3.9 V
DVDD DVSS –0.3 +3.9 V
DRVDD DRVSS –0.3 +3.9 V
Digital Outputs DRVSS –0.3 DRVDD + 0.3 V
SHP, SHD, DATACLK DVSS –0.3 DVDD + 0.3 V
CLPOB, PBLK DVSS –0.3 DVDD + 0.3 V
SCK, SL, SDATA DVSS –0.3 DVDD + 0.3 V
REFT, REFB, CCDIN AVSS –0.3 AVDD + 0.3 V
Junction Temperature 150 °C
Lead Temperature 300 °C
(10 sec)
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
Thermal Resistance
32-Lead LFCSP Package
θ
JA
= 27.7 °C/W
REV.
C
AD9945
–5–
PIN CONFIGURATION
TOP VIEW
24 REFB
23 REFT
22 CCDIN
21 AVSS
D2 1
D3 2
D4 3
32 D1
20 AVDD
19 SHD
18 SHP
17 CLPOB
D10 9
D11 10
DRVDD 11
DRVSS 12
DVDD 13
DATACLK 14
DVSS 15
PBLK 16
D5 4
D6 5
D7 6
D8 7
D9 8
31 D0
30 NC
29 NC
28 NC
27 SCK
26 SDATA
25 SL
AD9945
PIN 1
INDICATOR
PIN FUNCTION DESCRIPTIONS
Pin Number Mnemonic Type Description
1 to 10, 31, 32 D2 to D11, D0, D1 DO Digital Data Outputs
11 DRVDD P Digital Output Driver Supply
12 DRVSS P Digital Output Driver Ground
13 DVDD P Digital Supply
14 DATACLK DI Digital Data Output Latch Clock
15 DVSS P Digital Supply Ground
16 PBLK DI Preblanking Clock Input
17 CLPOB DI Black Level Clamp Clock Input
18 SHP DI CDS Sampling Clock for CCD’s Reference Level
19 SHD DI CDS Sampling Clock for CCD’s Data Level
20 AVDD P Analog Supply
21 AVSS P Analog Ground
22 CCDIN AI Analog Input for CCD Signal
23 REFT AO A/D Converter Top Reference Voltage Decoupling
24 REFB AO A/D Converter Bottom Reference Voltage Decoupling
25 SL DI Serial Digital Interface Load Pulse
26 SDATA DI Serial Digital Interface Data Input
27 SCK DI Serial Digital Interface Clock Input
28 to 30 NC NC Internally Pulled Down. Float or connect to GND.
TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
REV.
C
NOTES
1. IT IS RECOMMENDED THAT THE EXPOSED PAD BE
SOLDERED TO THE GROUND PLANE OF THE PCB.

AD9945KCPZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE 12-Bit 40 MHz CCD Signal Processor
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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