ADV7283 Data Sheet
Rev. A | Page 16 of 21
I
2
C PORT DESCRIPTION
The ADV7283 supports a 2-wire, I
2
C-compatible serial
interface. Two inputs, serial data (SDATA) and serial clock
(SCLK), carry information between the ADV7283 and the
system I
2
C master controller. The I
2
C port of the ADV7283
allows the user to set up and configure the decoder and to read
back captured VBI data.
The ADV7283 has a number of possible I
2
C slave addresses and
subaddresses (see the Register Maps section). The main map of
the ADV7283 has four possible slave addresses for read and write
operations, depending on the logic level of the ALSB pin (see
Table 12).
Table 12. Main Map I
2
C Address
ALSB Pin
R/
W
Bit
Slave Address
0 0 0x40 (write)
0 1 0x41 (read)
1 0 0x42 (write)
1 1 0x43 (read)
The ALSB pin controls Bit 1 of the slave address. By changing
the logic level of the ALSB pin, it is possible to control two
ADV7283 devices in an application without using the same I
2
C
slave address. The LSB (Bit 0) specifies either a read or write
operation: Logic 1 corresponds to a read operation, and Logic 0
corresponds to a write operation.
To control the device on the bus, a specific protocol is followed.
1. The master initiates a data transfer by establishing a start
condition, which is defined as a high to low transition on
SDATA while SCLK remains high, and indicates that an
address/data stream follows.
2. All peripherals respond to the start condition and shift the
next eight bits (the 7-bit address plus the R/
W
bit). The bits
are transferred from MSB to LSB.
3. The peripheral that recognizes the transmitted address
responds by pulling the data line low during the ninth
clock pulse; this is known as an acknowledge (ACK) bit.
4. All other devices withdraw from the bus and maintain an
idle condition. In the idle condition, the device monitors
the SDATA and SCLK lines for the start condition and the
correct transmitted address.
The R/
W
bit determines the direction of the data. Logic 0 on the
LSB of the first byte means that the master writes information
to the peripheral. Logic 1 on the LSB of the first byte means that
the master reads information from the peripheral.
The ADV7283 acts as a standard I
2
C slave device on the bus.
The data on the SDATA pin is eight bits long, supporting the 7-bit
address plus the R/
W
bit. The device has subaddresses to enable
access to the internal registers; therefore, it interprets the first
byte as the device address and the second byte as the starting
subaddress. The subaddresses auto-increment, allowing data to
be written to or read from the starting subaddress. A data transfer
is always terminated by a stop condition. The user can also access
any unique subaddress register individually without updating
all the registers.
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, they cause an immediate jump
to the idle condition. During a given SCLK high period, issue
only one start condition, one stop condition, or a single stop
condition followed by a single start condition. If the user issues
an invalid subaddress, the ADV7283 does not issue an
acknowledge and returns to the idle condition.
If the highest subaddress is exceeded in auto-increment mode,
one of the following actions is taken:
• In read mode, the register contents of the highest sub-
address continue to be output until the master device issues
a no acknowledge, which indicates the end of a read. A no
acknowledge condition occurs when the SDATA line is not
pulled low on the ninth pulse.
• In write mode, the data for the invalid byte is not loaded into
a subaddress register. The ADV7283 issues a no
acknowledge, and the device returns to the idle condition.
Figure 9. Bus Data Transfer
Figure 10. Read and Write Sequence
SDATA
SCLK
START ADDR ACK ACK DATA
ACK STOPSUBADDRESS
1–7 1–78
9 8 9 1–7 8 9
S P
R/W
12347-010
S
WRITE
SEQUENCE
SLAVE ADDR A(S) SUBADDRESS A(S)
DATA A(S)
DATA A(S)
P
S
READ
SEQUENCE
SLAVE ADDR SLAVE ADDRA(S) SUBADDRESS A(S)
S A(S) DATA A(M)
DATA A(M)
P
S = START BIT
P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A(S) = NO ACKNOWLEDGE BY SLAVE
A(M) = NO ACKNOWLEDGE BY MASTER
LSB = 1LSB = 0
12347-0
1
1
