LTC2351CUH-14#PBF Datasheet LTC2351IUH-14#PBF, LTC2351CUH-14#PBF, LTC2351HUH-14#PBF | P7-P9

LTC2351-14

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PIN FUNCTIONS

SDO (Pin 1): Three-State Serial Data Output. Each set

of six output data words represent the six analog input

channels at the start of the previous conversion. Data for

CH0 comes out ﬁ rst and data for CH5 comes out last. Each

data word comes out MSB ﬁ rst.

OGND (Pin 2): Ground Return for SDO Currents. Connect

to the solid ground plane.

(Pin 3): Power Supply for the SDO Pin. OV

must be no more than 300mV higher than V

and can

be brought to a lower voltage to interface to low voltage

logic families. The unloaded HIGH state at SDO is at the

potential of OV

CH0

(Pin 4): Noninverting Channel 0. CH0

operates

fully differentially with respect to CH0

–

with a 0V to 2.5V,

or ±1.25V differential swing and a 0V to V

absolute

input range.

CH0

–

(Pin 5): Inverting Channel 0. CH0

–

operates fully

differentially with respect to CH0

with a –2.5V to 0V,

or ±1.25V differential swing and a 0V to V

absolute

input range.

GND (Pins 6, 9, 12, 13, 16, 19): Analog Grounds. These

ground pins must be tied directly to the solid ground plane

under the part. Analog signal currents ﬂ ow through these

connections.

CH1

(Pin 7): Noninverting Channel 1. CH1

operates

fully differentially with respect to CH1

–

with a 0V to 2.5V,

or ±1.25V differential swing and a 0V to V

absolute

input range.

CH1

–

(Pin 8): Inverting Channel 1. CH1

–

operates fully

differentially with respect to CH1

with a –2.5V to 0V,

or ±1.25V differential swing and a 0V to V

absolute

input range.

CH2

(Pin 10): Noninverting Channel 2. CH2

operates

fully differentially with respect to CH2

–

with a 0V to 2.5V,

or ±1.25V differential swing and a 0V to V

absolute

input range.

CH2

–

(Pin 11): Inverting Channel 2. CH2

–

operates fully

differentially with respect to CH2

with a –2.5V to 0V,

or ±1.25V differential swing and a 0V to V

absolute

input range.

CH3

(Pin 14): Noninverting Channel 3. CH3

operates

fully differentially with respect to CH3

–

with a 0V to 2.5V,

or ±1.25V differential swing and a 0V to V

absolute

input range.

CH3

–

(Pin 15): Inverting Channel 3. CH3

–

operates fully

differentially with respect to CH3

with a –2.5V to 0V,

or ±1.25V differential swing and a 0V to V

absolute

input range.

CH4

(Pin 17): Noninverting Channel 4. CH4

operates

fully differentially with respect to CH4

–

with a 0V to 2.5V,

or ±1.25V differential swing and a 0V to V

absolute

input range.

CH4

–

(Pin 18): Inverting Channel 4. CH4

–

operates fully

differentially with respect to CH4

with a –2.5V to 0V, or

±1.25V differential swing and a 0V to V

absolute input

range.

CH5

(Pin 20): Noninverting Channel 5. CH5

operates

fully differentially with respect to CH5

–

with a 0V to 2.5V,

or ±1.25V differential swing and a 0V to V

absolute

input range.

CH5

–

(Pin 21): Inverting Channel 5. CH5

–

operates fully

differentially with respect to CH5

with a –2.5V to 0V, or

±1.25V differential swing and a 0V to V

absolute input

range.

GND (PIN 22): Analog Ground for Reference. Analog

ground must be tied directly to the solid ground plane

under the part. Analog signal currents ﬂ ow through this

connection. The 10μF reference bypass capacitor should

be returned to this pad.

REF

(Pin 23): 2.5V Internal Reference. Bypass to GND and

a solid analog ground plane with a 10μF ceramic capaci-

tor (or 10μF tantalum in parallel with 0.1μF ceramic). Can

be overdriven by an external reference voltage between

2.55V and V

, V

(Pin 24): 3V Positive Analog Supply. This pin sup-

plies 3V to the analog section. Bypass to the solid analog

ground plane with a 10μF ceramic capacitor (or 10μF

tantalum) in parallel with 0.1μF ceramic. Care should

be taken to place the 0.1μF bypass capacitor as close to

Pin 24 as possible. Pin 24 must be tied to Pin 25.

LTC2351-14

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PIN FUNCTIONS

(Pin 25): 3V Positive Digital Supply. This pin sup-

plies 3V to the logic section. Bypass to DGND pin and

solid analog ground plane with a 10μF ceramic capacitor

(or 10μF tantalum in parallel with 0.1μF ceramic). Keep

in mind that internal digital output signal currents ﬂ ow

through this pin. Care should be taken to place the 0.1μF

bypass capacitor as close to Pin 25 as possible. Pin 25

must be tied to Pin 24.

SEL2 (Pin 26): Most Signiﬁ cant Bit Controlling the

Number of Channels Being Converted. In combination

with SEL1 and SEL0, 000 selects just the ﬁ rst channel

(CH0) for conversion. Incrementing SELx selects addi-

tional channels(CH0–CH5) for conversion. 101, 110 or 111

select all six channels for conversion. Must be kept in a

ﬁ xed state during conversion and during the subsequent

conversion to read data.

SEL1 (Pin 27): Middle Signiﬁ cant Bit Controlling the

Number of Channels Being Converted. In combination

with SEL0 and SEL2, 000 selects just the ﬁ rst channel

(CH0) for conversion. Incrementing SELx selects additional

channels for conversion. 101, 110 or 111 select all six

channels (CH0–CH5) for conversion. Must be kept in a

ﬁ xed state during conversion and during the subsequent

conversion to read data.

SEL0 (Pin 28): Least Signiﬁ cant Bit Controlling the

Number of Channels Being Converted. In combination

with SEL1 and SEL2, 000 selects just the ﬁ rst channel

(CH0) for conversion. Incrementing SELx selects addi-

tional channels for conversion. 101, 110 or 111 select all

six channels (CH0–CH5) for conversion. Must be kept in

a ﬁ xed state during conversion and during the subsequent

conversion to read data.

BIP (Pin 29): Bipolar/Unipolar Mode. The input dif-

ferential range is 0V – 2.5V when BIP is LOW, and it is

±1.25V when BIP is HIGH. Must be kept in ﬁ xed state

during conversion and during subsequent conversion to

read data. When changing BIP between conversions the

full acquisition time must be allowed before starting the

next conversion. The output data is in 2’s complement

format for bipolar mode and straight binary format for

unipolar mode.

CONV (Pin 30): Convert Start. Holds the six analog input

signals and starts the conversion on the rising edge. Two

CONV pulses with SCK in ﬁ xed HIGH or ﬁ xed LOW state

starts nap mode. Four or more CONV pulses with SCK in

ﬁ xed HIGH or ﬁ xed LOW state starts sleep mode.

DGND (Pin 31): Digital Ground. This ground pin must be

tied directly to the solid ground plane. Digital input signal

currents ﬂ ow through this pin.

SCK (Pin 32): External Clock Input. Advances the con-

version process and sequences the output data at SD0

(Pin1) on the rising edge. One or more SCK pulses wake

from sleep or nap power saving modes. 16 clock cycles

are needed for each of the channels that are activated by

SELx (Pins 26, 27, 28), up to a total of 96 clock cycles

needed to convert and read out all six channels.

Exposed Pad (Pin 33): GND. Must be tied directly to the

solid ground plane.

LTC2351-14

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BLOCK DIAGRAM

OGND

SD0

–

S & H

–

12 13

S & H

EXPOSED PAD GND V

REF

10μF

CH0

–

CH0

CH1

–

CH1

–

S & H

–

S & H

CH2

–

CH2

CH3

–

CH3

–

S & H

–

S & H

CH4

–

CH4

CH5

–

CH5

10μF

0.1μF

DGND

SCK

CONV

SEL2

SEL1 SEL0

THREE-

STATE

SERIAL

OUTPUT

PORT

MUX

2.5V

REFERENCE

TIMING

LOGIC

235114 BD

1.5Msps

14-BIT ADC

14-BIT LATCH 5

14-BIT LATCH 4

14-BIT LATCH 3

14-BIT LATCH 2

14-BIT LATCH 1

14-BIT LATCH 0

26 27

BIP

29 28 31

2233

0.1μF

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

LTC2351CUH-14#PBF

Mfr. #:

Buy LTC2351CUH-14#PBF

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 14-Bit, 6-Channel 1.5Msps simultaneous Sampling ADC

Lifecycle:

New from this manufacturer.

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LTC2351CUH-14#PBF

LTC2351CUH-14#PBF

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