LTC2351-14
16
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APPLICATIONS INFORMATION
POWER-DOWN MODES
Upon power-up, the LTC2351-14 is initialized to the
active state and is ready for conversion. The nap and sleep
mode waveforms show the power down modes for the
LTC2351-14. The SCK and CONV inputs control the power
down modes (see Timing Diagrams). Two rising edges at
CONV, without any intervening rising edges at SCK, put
the LTC2351-14 in nap mode and the power consumption
drops from 16.5mW to 4.5mW. The internal reference
remains powered in nap mode. One or more rising edges
at SCK wake up the LTC2351-14 very quickly and CONV
can start an accurate conversion within a clock cycle.
Four rising edges at CONV, without any intervening rising
edges at SCK, put the LTC2351-14 in sleep mode and the
power consumption drops from 16.5mW to 12μW. One
or more rising edges at SCK wake up the LTC2351-14 for
operation. The internal reference (V
REF
) takes 2ms to
slew and settle with a 10μF load. Using sleep mode more
frequently compromises the accuracy of the output data.
Note that for slower conversion rates, the nap and sleep
modes can be used for substantial reductions in power
consumption.
DIGITAL INTERFACE
The LTC2351-14 has a 3-wire SPI (serial peripheral
interface). The SCK and CONV inputs and SDO output
implement this interface. The SCK and CONV inputs
accept swings from 3V logic and are TTL compatible, if the
logic swing does not exceed V
DD
. A detailed description
of the three serial port signals follows:
Conversion Start Input (CONV)
The rising edge of CONV starts a conversion, but subse-
quent rising edges at CONV are ignored by the LTC2351-14
until the following 96 SCK rising edges have occurred. The
duty cycle of CONV can be arbitrarily chosen to be used as
a frame sync signal for the processor serial port. A simple
approach to generate CONV is to create a pulse that is one
SCK wide to drive the LTC2351-14 and then buffer this
signal to drive the frame sync input of the processor serial
port. It is good practice to drive the LTC2351-14 CONV
input fi rst to avoid digital noise interference during the
sample-to-hold transition triggered by CONV at the start
of conversion. It is also good practice to keep the width
of the low portion of the CONV signal greater than 15ns
to avoid introducing glitches in the front end of the ADC
just before the sample-and-hold goes into hold mode at
the rising edge of CONV.
Minimizing Jitter on the CONV Input
In high speed applications where high amplitude sine waves
above 100kHz are sampled, the CONV signal must have
as little jitter as possible (10ps or less). The square wave
output of a common crystal clock module usually meets
this requirement. The challenge is to generate a CONV
signal from this crystal clock without jitter corruption from
other digital circuits in the system. A clock divider and
any gates in the signal path from the crystal clock to the
CONV input should not share the same integrated circuit
with other parts of the system. The SCK and CONV inputs
should be driven fi rst, with digital buffers used to drive
the serial port interface. Also note that the master clock
in the DSP may already be corrupted with jitter, even if it
comes directly from the DSP crystal. Another problem with
high speed processor clocks is that they often use a low
cost, low speed crystal (i.e., 10MHz) to generate a fast,
but jittery, phase-locked loop system clock (i.e., 40MHz).
The jitter in these PLL-generated high speed clocks can be
several nanoseconds. Note that if you choose to use the
frame sync signal generated by the DSP port, this signal
will have the same jitter of the DSP’s master clock.
The Typical Application on the last page of this datasheet
shows a circuit for level shifting and squaring the output
from an RF signal generator or other low jitter source. A
single D-type fl ip-fl op is used to generate the CONV signal
to the LTC2351-14. Re-timing the master clock signal
eliminates clock jitter introduced by the controlling device
(DSP, FPGA, etc.) Both the inverter and fl ip-fl op must be
treated as analog components and should be powered
from a clean analog supply.
Serial Clock Input (SCK)
The rising edge of SCK advances the conversion process
and also udpates each bit in the SDO data stream. After
CONV rises, the third rising edge of SCK sends out up to
six sets of 14 data bits, with the MSB sent fi rst. A simple
approach is to generate SCK to drive the LTC2351-14 fi rst
