NCP3063, NCP3063B, NCV3063
http://onsemi.com
14
Figure 27. Typical Buck Application Schematic with External PMOS Transistor
IC1 NCP3063
5
36
4
8
7
1
2
R3
V
IN
= 8 − 19 V
V
OUT
= 3V3/3 A
+
COMP
TC
GND
N.C. SWC
SWE
V
CC
I
PK
1k
C2
100n
C1
0V GND
C6
100n
C7
R8
470
C5
2n2
R6
22k
R2 1k7
R1 50m
10m
L1
6
1
Q2
NTGS4111P
C4
6n8
R5
1k
D1
1N5822
+
4
3
2
5
T1
BC848CPD
330m 330m
60
65
70
75
80
85
90
95
100
0 0.5 1 1.5 2 2.5
Figure 28. NCP3063 Efficiency vs. Output Current for
Buck External PMOS at V
out
= 3.3 V, f = 220 kHz,
T
A
= 255C
EFFICIENCY (%)
OUTPUT LOAD (Adc)
V
IN
= 8 V
V
IN
= 18 V
Figure 27 shows typical buck configuration with external
PMOS transistor. The principle of driving the Q2 gate is the
same as shown in Figure 27.
Resistor R6 connected between TC and SWE pin provides
a pulsed feedback voltage. It is recommended to use this
pulsed feedback approach on applications with a wide input
voltage range, applications with the input voltage over
+12 V or applications with tighter specifications on output
ripple. The suitable value of resistor R6 is between
10k − 68k. The pulse feedback approach increases the
operating frequency by about 20%. It also creates more
regular switching waveforms with constant operating
frequency which results in lower output ripple voltage and
improved efficiency.
The pulse feedback resistor value has to be selected so that
the capacitor charge and discharge currents as listed in the
electrical characteristic table, are not exceeded. Improper
selection will lead to errors in the oscillator operation. The
maximum voltage at the TC Pin cannot exceed 1.4 V when
implementing pulse feedback.