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AD7823YRZ

P1-P3P4-P6P7-P9P10-P12
AD7823
–3–
REV. C
TIMING CHARACTERISTICS
1, 2
Parameter V
DD
= 5 V ⴞ 10% V
DD
= 3 V ⴞ 10% Unit Conditions/Comments
t
1
55µs (max) Conversion Time Mode 1 Operation (High Speed Mode)
t
2
20 20 ns (min) CONVST Pulsewidth
t
3
25 25 ns (min) SCLK High Pulsewidth
t
4
25 25 ns (min) SCLK Low Pulsewidth
t
5
3
5 5 ns (min) CONVST Rising Edge to SCLK Rising Edge Set-Up Time
t
6
3
10 10 ns (max) SCLK Rising Edge to D
OUT
Data Valid Delay
t
7
3
5 5 ns (max) Data Hold Time after Rising Edge SCLK
t
8
3, 4
20 20 ns (max) Bus Relinquish Time after Falling Edge of SCLK
10 10 ns (min)
t
POWERUP
1.5 1.5 µs (max) Power-Up Time
NOTES
1
Sample tested to ensure compliance.
2
See Figures 14, 15 and 16.
3
These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V
DD
= 5 V ± 10% and
0.4 V or 2 V for V
DD
= 3 V ± 10%.
4
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the Timing Characteristics, t
8
, is the true bus relinquish time
of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
(–40ⴗC to +125ⴗC, unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS*
(T
A
= 25°C unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to GND
(CONVST, SCLK) . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Digital Output Voltage to GND
(D
OUT
) . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
V
REF
to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Analog Inputs
(V
IN+
, V
IN–
) . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 125°C/W
θ
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 50°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . 260°C
I
OL
200mA
I
OH
200␮A
1.6V
C
L
50pF
TO
OUTPUT
PIN
Figure 1. Load Circuit for Digital Output Timing Specifications
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 160°C/W
θ
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 56°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
MicroSOIC Package, Power Dissipation . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 206°C/W
θ
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 44°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Linearity Temperature Branding Package
Model Error Range Information Option*
AD7823YN ± 1 LSB –40°C to +125°C N-8
AD7823YR ± 1 LSB –40°C to +125°C SO-8
AD7823YRM ± 1 LSB –40°C to +125°C C2Y RM-8
*N = plastic DIP; RM = microSOIC; SO = small outline IC (SOIC).
AD7823
–4–
REV. C
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Description
1 CONVST Convert Start. Falling edge puts the track-and-hold into hold mode and initiates a conversion.
A rising edge on the CONVST pin enables the serial port of the AD7823. This is useful in
multipackage applications where a number of devices share the same serial bus. The state of
this pin at the end of conversion also determines whether the part is powered down or not.
See Operating Modes section of this data sheet.
2V
IN+
Positive input of the pseudo differential analog input.
3V
IN–
Negative input of the pseudo differential analog input.
4 GND Ground reference for analog and digital circuitry.
5V
REF
External reference is connected here.
6D
OUT
Serial data is shifted out on this pin.
7 SCLK Serial Clock. An external serial clock is applied here.
8V
DD
Positive Supply Voltage 2.7 V to 5.5 V.
PIN CONFIGURATION
DIP/SOIC/microSOIC
1
2
3
4
8
7
6
5
TOP VIEW
(Not to Scale)
AD7823
CONVST
V
IN+
V
IN–
GND
V
DD
SCLK
D
OUT
V
REF
AD7823
–5–
REV. C
The AD7823 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second and third order terms are of different
significance. The second order terms are usually distanced in
frequency from the original sine waves while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified sepa-
rately. The calculation of the intermodulation distortion is as
per the THD specification where it is the ratio of the rms sum of
the individual distortion products to the rms amplitude of the
fundamental expressed in dBs.
Relative Accuracy
Relative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
Differential Nonlinearity
This is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (0000 . . . 000)
to (0000 . . . 001) from the ideal, i.e., AGND + 1 LSB.
Gain Error
This is the deviation of the last code transition (1111 . . . 110)
to (1111 . . . 111) from the ideal (i.e., V
REF
– 1 LSB) after the
offset error has been adjusted out.
Track/Hold Acquisition Time
Track/hold acquisition time is the time required for the output
of the track/hold amplifier to reach its final value, within
± 1/2 LSB, after the end of conversion (the point at which the
track/hold returns to track mode). It also applies to situations
where there is a step input change on the input voltage applied
to the V
IN+
input of the AD7823. It means that the user must
wait for the duration of the track/hold acquisition time, after the
end of conversion or after a step input change to V
IN
, before
starting another conversion to ensure that the part operates to
specification.
TERMINOLOGY
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (f
S
/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal to (noise + distortion)
ratio for an ideal N-bit converter with a sine wave input is
given by:
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
Thus for an 8-bit converter, this is 50 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7823 it is defined as:
THD (dB) = 20 log
V
2
2
+ V
3
2
+ V
4
2
+ V
5
2
+ V
6
2
V
1
where V
1
is the rms amplitude of the fundamental and V
2
, V
3
,
V
4
, V
5
and V
6
are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f
S
/2 and excluding dc) to the rms value of
the fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
parts where the harmonics are buried in the noise floor, it
will be a noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For example, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
Typical Performance Characteristics
THROUGHPUT – kSPS
10
0
0.01
030
POWER – mW
10
0.1
20 40 50
Figure 2. Power vs. Throughput
FREQUENCY BINS
0
–70
–100
dBs
–10
–60
–80
–90
–30
–50
–20
–40
1
23
45
67
89
111
133
155
177
199
221
243
265
287
309
331
353
375
397
419
441
463
485
507
529
551
573
595
617
639
661
683
705
727
749
771
793
815
837
859
881
903
925
947
969
991
1013
AD7823
2048 POINT FFT
SAMPLING 136.054
f
IN
29.961
Figure 3. AD7823 SNR
P1-P3P4-P6P7-P9P10-P12

AD7823YRZ

Mfr. #:
Buy AD7823YRZ
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 2.7V-5.5V 4.5ms 8B
Lifecycle:
New from this manufacturer.
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