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X9401WS24IZ-2.7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
19
FN8190.5
September 14, 2015
X9401
Package Outline Drawing
M24.3
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC)
Rev 2, 3/11
TOP VIEW
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
2. Package length does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
3. Package width does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm
(0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions in
( ) are not necessarily exact.
8. This outline conforms to JEDEC publication MS-013-AD ISSUE C.
SIDE VIEW “A”
SIDE VIEW “B”
TYPICAL RECOMMENDED LAND PATTERN
INDEX
AREA
24
123
SEATING PLANE
DETAIL "A"
x 45°
7.60 (0.299)
7.40 (0.291)
0.75 (0.029)
0.25 (0.010)
10.65 (0.419)
10.00 (0.394)
1.27 (0.050)
0.40 (0.016)
15.60 (0.614)
15.20 (0.598)
2.65 (0.104)
2.35 (0.093)
0.30 (0.012)
0.10 (0.004)
1.27 (0.050)
0.51 (0.020)
0.33 (0.013)
0.32 (0.012)
0.23 (0.009)
8°
0°
1.981 (0.078)
9.373 (0.369)
0.533 (0.021)1.27 (0.050)
20
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8190.5
September 14, 2015
X9401
Thin Shrink Small Outline Package Family (TSSOP)
MDP0044
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
SYMBOL
MILLIMETERS
TOLERANCE14 LD 16 LD 20 LD 24 LD 28 LD
A 1.20 1.20 1.20 1.20 1.20 Max
A1 0.10 0.10 0.10 0.10 0.10 ±0.05
A2 0.90 0.90 0.90 0.90 0.90 ±0.05
b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06
c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06
D 5.00 5.00 6.50 7.80 9.70 ±0.10
E 6.40 6.40 6.40 6.40 6.40 Basic
E1 4.40 4.40 4.40 4.40 4.40 ±0.10
e 0.65 0.65 0.65 0.65 0.65 Basic
L 0.60 0.60 0.60 0.60 0.60 ±0.15
L1 1.00 1.00 1.00 1.00 1.00 Reference
Rev. F 2/07
NOTES:
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

X9401WS24IZ-2.7

Mfr. #:
Buy X9401WS24IZ-2.7
Manufacturer:
Renesas / Intersil
Description:
Digital Potentiometer ICs X9401WS24IZ QD DCP 10KOHM 64 TAPS SPI
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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