MAX6652
_______________________________________________________________________________________ 9
Temperature Sensor and System Monitor
in a 10-Pin µMAX
Default Mode
An interrupt is initiated when temperature exceeds
T
HOT
(address 39Ah). The interrupt is cleared only by
reading the interrupt status register. An interrupt will
continue to be generated on subsequent measure-
ments until temperature goes below T
HYST
(address
3Ah).
One-Time Interrupt Mode
An interrupt is initiated when temperature exceeds
T
HOT
(address 39Ah). The interrupt is cleared only by
reading the interrupt status register. The next interrupt
is then initiated when temperature falls below the T
HYST
(address 3Ah).
Comparator Mode
An interrupt is initiated when temperature exceeds
T
HOT
(address 39Ah). The ALERT output will remain
asserted low until the temperature goes below T
HOT
.
Reading the interrupt status register will not clear the
ALERT output or interrupt status bit in the register. The
interrupt will continue to be generated on subsequent
measurements until temperature falls below T
HOT
.
Figure 1 shows successive interrupts and clears using
a temperature fault as an example.
I
2
C-Compatible/SMBus Digital Interface
From a software perspective, the MAX6652 appears as
a set of byte-wide registers that contain voltage and
temperature data, alarm threshold values, or control
bits.
The device employs four standard I
2
C-compatible/
SMBus protocols: write byte, read byte, send byte, and
receive byte (Figures 2, 3, 4).
Slave Address
The device address can be set to one of four different
values by pin strapping ADD to GND, SDA, SCL, or
V
CC
, so more than one MAX6652 can reside on the
same bus without address conflicts (Table 1). The
address pin state is checked at the beginning of each
I
2
C-compatible/SMBus transaction and so is insensitive
to glitches on V
CC
. Any address code can also be writ-
ten to the serial address register and will overwrite the
code set by connecting the ADD pin until the MAX6652
is taken through a POR cycle.
The MAX6652 also responds to the SMBus alert
response address (see Alert Response Address).
Alert Response Address
The SMBus alert response interrupt pointer provides
quick fault identification for simple slave devices that
lack the complex, expensive logic needed to be a bus
master. Usually the ALERT outputs of several slave
devices are wired-ORed to the same interrupt input of
the host master. Upon receiving an interrupt signal, the
host master can broadcast a receive byte transmission
(Figure 2) with the alert response address (0001 1000).
Then, any slave device that generated an interrupt
attempts to identify itself by putting its own address on
the bus.
The alert response can activate several different slave
devices simultaneously, similar to the I
2
C general call. If
more than one slave attempts to respond, bus arbitra-
tion rules apply, and the device with the lower address
code wins. The losing device does not generate an
acknowledge signal and continues to hold the interrupt
line low until serviced. The MAX6652 does not automat-
ically clear its ALERT when it responds to an alert
response address. The host master must then clear or
mask the ALERT by reading the interrupt status regis-
ter, writing to the interrupt mask register, or setting bit 1
of the configuration register to 0 before it can identify
other slaves generating an interrupt.
Command Byte Functions
The 8-bit command byte register (Table 1) is the master
index that points to the other data, configuration, limits,
and address registers within the MAX6652. The func-
tions of those other registers are described below.
Configuration Byte Functions
The configuration register (Table 4) is a read-write reg-
ister with several functions:
Bit 0 puts the MAX6652 into software standby mode
(STOP) or autoconvert (START) mode. The 2-wire inter-
face is still active in the standby mode. All voltage and
temperature limits should be set before setting this bit
to 1.
Bit 1 enables and disables the ALERT output. Setting
this bit to 1 enables the ALERT output.
Bit 2 is reserved.
Bit 3 clears the ALERT output and stops the monitoring
loop when set to 1. Clearing the output will not affect
the contents of the interrupt status registers.
Bit 4 sets the analog-to-digital conversion speed to
minimize interference from power-line frequencies.
Setting this bit to 1 can improve accuracy when the
power-line frequency is 50Hz. When the power-line fre-
quency is 60Hz, bit 4 should be 0.
Bit 5 reduces the oversampling ratio in the ADC from 8
to 2. This reduces the monitoring cycle time by a factor
of 4 to typically 50ms at the cost of reduced noise
rejection.
