LTC2444CUHF#PBF Datasheet LTC2449IUHF#PBF, LTC2448CUHF#PBF, LTC2448IUHF#PBF | P10-P12

LTC2444/LTC2445/

LTC2448/LTC2449

2444589fc

For more information www.linear.com/LTC2444

applicaTions inForMaTion

clears all internal registers. The conversion immediately

following a POR is performed on the input channel IN

= CH0, IN

–

= CH1 at an OSR = 256 in the 1X mode. Fol-

lowing the POR signal, the LTC2444/LTC2445/LTC2448/

LTC2449 start a normal conversion cycle and follow the

succession of states described above. The first conversion

result following POR is accurate within

the specifications

of the device if the power supply voltage is restored within

the operating range (4.5V to 5.5V) before the end of the

POR time interval.

Reference Voltage Range

These converters accept a truly differential external

reference voltage. The absolute/common mode voltage

specification for the REF

and REF

–

pins covers the entire

range from GND to V

. For correct converter operation, the

REF

pin must always be more positive than the REF

–

pin.

The LTC2444/LTC2445/LTC2448/LTC2449 can accept a

differential reference voltage from 0.1V to V

. The con-

verter output noise is determined by the thermal noise of

the front-end circuits, and as such, its value in microvolts

is nearly constant with reference voltage. A decrease in

reference voltage will not significantly improve the con

verter’s effective resolution. On the other hand, a reduced

reference voltage will improve the converter’s overall INL

per

formance.

Input V

oltage Range

Refer to Figure 4. The analog input is truly differential with an

absolute/common mode range for the CH0 to CH15 and COM

input pins extending from GND – 0.3V to V

+ 0.3V. Outside

these limits, the ESD protection devices begin to turn on

and the errors due to input leakage current increase rap-

idly. Within these limits, the LTC2444/LTC2445/LTC2448/

LTC2449 convert the bipolar differential input signal, V

– IN

–

(where IN

and IN

–

are the selected input chan-

nels),

from –FS = –0.5 • V

REF

to +FS = 0.5 • V

REF

where

REF

= REF

– REF

–

. Outside this range, the converter

indicates the overrange or the underrange condition using

distinct output codes.

MUXOUT/ADCIN

There are two differences between the LTC2444/LTC2448

and the LTC2445/LTC2449. The first is the RMS noise

performance. For a given OSR, the LTC2445/LTC2449

noise level is approximately √2 times lower (0.5 effective

bits)than that of the LTC2444/LTC2448.

The second difference is the LTC2445/LTC2449 includes

MUXOUT/ADCIN pins. These pins enable an external buf

fer or gain block to be inserted between the output of the

multiplexer and the input to the ADC. Since the buffer is

driven by the output of the multiplexer

, only one circuit is

Figure 3. SDI Speed/Resolution, Channel Selection, and Data Output Timing

MSB

BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 0

LSB

Hi-Z

2444589 F03

SIG

BIT 29

“0”

BIT 30

EOC

Hi-Z

SCK

SDI

SDO

BUSY

BIT 31

1 0 EN SGL A2 A1 A0 OSR3 OSR2 OSR1 OSR0 TWOXODD

1 2 3 4 5 6 7 8 9 10 11 12 13 14 32

LTC2444/LTC2445/

LTC2448/LTC2449

2444589fc

For more information www.linear.com/LTC2444

required for all 16 input channels. Additionally, the transpar-

ent calibration feature of the LTC244X family automatically

removes the offset errors of the external buffer.

In order to achieve optimum performance, the MUXOUT

and ADCIN pins should not be shorted together. In applica

tions where the MUXOUT and ADCIN need to be shorted

together

, the LTC2444/LTC2448 should be used because

the MUXOUT and ADCIN are internally connected for

optimum per

formance.

Output Data Format

The LTC2444/LTC2445/LTC2448/LTC2449 serial output

data stream is 32 bits long. The first 3 bits represent sta

tus information indicating the sign and conversion state.

The next 24 bits are the conversion result, MSB first. The

remaining 5 bits are sub LSBs beyond the 24-bit level that

may be included in averaging or discarded without loss of

resolution. In the case of ultrahigh resolution modes, more

than 24 effective bits of per

formance are possible (see

Table 5). Under these conditions, sub LSBs are included

in the conversion result and represent useful information

beyond the 24-bit level. The third and fourth bit together

are also used to indicate an underrange condition (the

differential input voltage is below –FS) or an overrange

condition (the differential input voltage is above +FS).

Bit 31 (first output bit) is the end of conversion (EOC)

indicator. This bit is available at the SDO pin during the

conversion and sleep states whenever the CS pin is LOW.

This bit is HIGH during the conversion and goes LOW

when the conversion is complete.

Bit 30 (second output bit) is a dummy bit (DMY) and is

always LOW.

Bit 29 (third output bit) is the conversion result sign

indicator (SIG). If V

is >0, this bit is HIGH. If V

is <0,

this bit is LOW.

Bit 28 (fourth output bit) is the most significant bit (MSB) of

the result. This bit in conjunction with Bit 29 also provides

the underrange or overrange indication. If both Bit 29 and

Bit 28 are HIGH, the differential input voltage is above +FS.

If both Bit 29 and Bit 28 are LOW, the differential input

voltage is below –FS.

applicaTions inForMaTion

+ 0.3V

GND

–0.3V

GND

–0.3V

(a) Arbitrary (b) Fully Differential

(d) Pseudo-Differential Unipolar

IN– or COM Grounded

IN– or COM Biased

REF

–V

REF

–V

REF

–V

REF

Selected IN

–

Ch or COM

2444589 F04

Figure 4. Input Range

LTC2444/LTC2445/

LTC2448/LTC2449

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For more information www.linear.com/LTC2444

The function of these bits is summarized in Table 1.

Table 1. LTC2444/LTC2445/LTC2448/LTC2449 Status Bits

INPUT RANGE

BIT 31

EOC

BIT 30

DMY

BIT 29

SIG

BIT 28

MSB

≥ 0.5 • V

REF

0 0 1 1

0V ≤ V

< 0.5 • V

REF

0 0 1 0

–0.5 • V

REF

≤ V

< 0V 0 0 0 1

< –0.5 • V

REF

0 0 0 0

Bits 28 to 5 are the 24-bit conversion result MSB first.

Bit 5 is the least significant bit (LSB).

Bits 4 to 0 are sub LSBs below the 24-bit level. Bits 4 to

0 may be included in averaging or discarded without loss

of resolution.

Data is shifted out of the SDO pin under control of the

serial clock (SCK), see Figure 3. Whenever CS is HIGH,

SDO remains high impedance and SCK is ignored.

In order to shift the conversion result out of the device,

CS must first be driven LOW. EOC is seen at the SDO pin

of the device once CS is pulled LOW. EOC changes real

time from HIGH to LOW at the completion of a conversion.

This signal may be used as an interrupt for an external

microcontroller. Bit 31 (EOC) can be captured on the first

rising edge of SCK. Bit 30 is shifted out of the device on

the first falling edge of SCK. The final data bit (Bit 0) is

shifted out on the falling edge of the 31st SCK and may

be latched on the rising edge of the 32nd SCK pulse. On

the falling edge of the 32nd SCK pulse, SDO goes HIGH

indicating the initiation of a new conversion cycle. This

bit serves as EOC (Bit 31) for the next conversion cycle.

Table 2 summarizes the output data format.

As long as the voltage on the IN

and IN

–

pins is main-

tained within the –0.3V to (V

+ 0.3V) absolute maximum

operating range, a conversion result is generated for any

differential input voltage V

from –FS = –0.5 • V

REF

+FS = 0.5 • V

REF

. For differential input voltages greater

than +FS, the conversion result is clamped to the value

corresponding to the +FS + 1LSB. For differential input

voltages below –FS, the conversion result is clamped to

the value corresponding to –FS – 1LSB.

SERIAL INTERFACE PINS

The LTC2444/LTC2445/LTC2448/LTC2449 transmit the

conversion results and receive the start of conversion

command through a synchronous 3- or 4-wire interface.

During the conversion and sleep states, this interface can

be used to assess the converter status and during the

data output state it is used to read the conversion result

and program the speed, resolution and input channel.

applicaTions inForMaTion

Table 2. LTC2444/LTC2445/LTC2448/LTC2449 Output Data Format

DIFFERENTIAL INPUT VOLTAGE

BIT 31

EOC

BIT 30

DMY

BIT 29

SIG

BIT 28

MSB

BIT 27 BIT 26 BIT 25 … BIT 0

* ≥ 0.5 • V

REF

** 0 0 1 1 0 0 0 … 0

0.5 • V

REF

** – 1LSB 0 0 1 0 1 1 1 … 1

0.25 • V

REF

** 0 0 1 0 1 0 0 … 0

0.25 • V

REF

** – 1LSB 0 0 1 0 0 1 1 … 1

0 0 0 1 0 0 0 0 … 0

–1LSB 0 0 0 1 1 1 1 … 1

–0.25 • V

REF

** 0 0 0 1 1 0 0 … 0

–0.25 • V

REF

** – 1LSB 0 0 0 1 0 1 1 … 1

–0.5 • V

REF

** 0 0 0 1 0 0 0 … 0

* < –0.5 • V

REF

** 0 0 0 0 1 1 1 … 1

*The differential input voltage V

= IN

– IN

–

. **The differential reference voltage V

REF

= REF

– REF

–

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LTC2444CUHF#PBF

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 24-Bit 4-ch. Diff., High Speed Delta-Sigma ADC

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LTC2444CUHF#PBF

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