NB3H83905CDGEVB
http://onsemi.com
4
supply voltages. Transitions Edges should about 250 ps or
use TTC, Time transition Convertor, such as Agilent 14534
(250 ps) or an equivalent. Do not drive XTALOUT.
Termination of the signal generator may be needed with 50
Ohms to SMA ground.
For Crystal operation use a fundamental Parallel
Resonant crystal (see Datasheet Table 3) from 3 MHz to 40
MHz across pins 1 and 16. The Crystal mount is located on
the back of the board and permanently connected to the
device inputs by traces. Crystal Load capacitance (C1 and
C2) values should consider all parasitic capacitances.
Datasheet Figure 1 shows the typical NB3H83905C device
crystal interface using a parallel resonant crystal. The
frequency accuracy can be fine tuned by adjusting the C1
and C2 values. For example, a parallel crystal with loading
capacitance C
L = 18 pF would use C1 = 15 pF and C2 = 15
pF as initial values. These values may be adjusted to fine
tune frequency accuracy. Increasing the C1 and C2 values
will reduce the operational frequency.
Enable 1 and 2 (see Datasheet Table 2) levels must be
shifted according to the supply voltages. Open default
condition will force a HIGH (enabled) due to an internal
pullup resistor to VCC.
3.) Outputs:
Connect LVCMOS outputs to the oscilloscope with
matched cables. NOTE: THE READINGS OF THE
OUTPUT VOLTAGE LEVELS WILL BE OFFSET. With
this split supply, the device outputs will be parallel
terminated by the oscilloscope (or frequency counter) input
module’s internal 50 Ohms to GND impedance.
APPENDIX 1: DEVICE PIN TO BOARD CONNECTION INFORMATION
(see current Datasheet)
Table 2. Device Pins to Board Connection
Device Pin Board
Connection
Name I/O Description
1 XTAL_OUT Crystal
Interface
Oscillator Output to drive Crystal
2 ENABLE 2 LVTTL /
LVCMOS
Input
Synchronous Enable Input for BCLK5 Output. Switches only
when HIGH. Open default condition HIGH due to an internal pul-
lup resistor to VCC.
3, 7, 11 DUTGND or
DUTGND_TP
GND GND GND Supply pins. All VDD and VDDO pins must be externally
connected to power supply to guarantee proper operation.
4, 6, 8, 10,
12, 14
BCLK0, 1, 2,
3, 4, 5
BCLK0, 1, 2,
3, 4, 5
LVCMOS
Outputs
Buffered Clock outputs
5, 13 VDDO VDDO POWER Output Positive Supply pins. All VDD and VDDO pins must be
externally connected to power supply to guarantee proper opera-
tion. Bypass with 0.01 mF cap to GND.
9 VDD or
VDD_TP
VDD POWER Output Positive Supply pins. All VDD and VDDO pins must be
externally connected to power supply to guarantee proper opera-
tion. Bypass with 0.01 mF cap to GND.
15 EN1 ENABLE 1 LVTTL /
LVCMOS
Input
Synchronous Enable Input for BCLK0/1/2/3/4 Output block.
Switches only when HIGH. Open default condition HIGH due to
an internal pullup resistor to VCC
16 XTALIN XTAL_IN/
CLK
Crystal
Interface
Oscillator Input from Crystal. Single ended Clock Input.
SMAGND or
SMAGND_TP
SMAGND SMA connectors GND. Should be connected equipment GND.
