LTC4210 -1/LTC4210 -2
16
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APPLICATIONS INFORMATION
Normal Mode/External Timer Control
Whenever the TIMER pin voltage drops below the COMP1
threshold, but is not in reset mode, the TIMER enters
normal (100µA source) mode with an equivalent 7k resis
-
tive pull-down. Table 1 shows the relationship of t
INITIAL
,
t
CBDELAY
, t
COOLOFF
vs C
TIMER
.
If the TIMER pin is pulled beyond the COMP2 threshold,
the GATE pin is pulled to ground immediately. This allows
the TIMER pin to be used for overvoltage detection, see
Figure 11.
Externally forcing the TIMER pin below the COMP1
threshold will reset the TIMER to normal mode. During
overvoltage detection, the TIMERs 100µA pull-down
current will continue to be on if (V
CC
SENSE) voltage is
below 50mV. If the (V
CC
SENSE) voltage exceeds 50mV
during the overvoltage detection, the TIMER current will be
the same as described for latched-off or autoretry mode.
See the section OVERVOLTAGE DETECTION USING TIMER
PIN for details of the application.
Power-Off Cycle
The system can be reset by toggling the ON pin low for
more than 30µs as shown at time point 7 of Figure 3. The
GATE pin is pulled to ground. The TIMER capacitor is also
discharged to ground. C
LOAD
discharges through the load.
Alternatively, the TIMER pin can be externally driven above
the COMP2 threshold to turn off the GATE pin.
POWER MOSFET SELECTION
Power MOSFETs can be classified by R
DSON
at V
GS
gate drive
ratings of 10V, 4.5V, 2.5V and 1.8V. Use the typical curves
∆V
GATE
vs Supply Voltage and ∆V
GATE
vs Temperature to
determine whether the gate drive voltage is adequate for
the selected MOSFET at the operating voltage.
In addition, the selected MOSFET should fulfill two V
GS
criteria:
1. Positive V
GS
absolute maximum rating > LTC4210
maximum ∆V
GATE
, and
2. Negative V
GS
absolute maximum rating > supply volt-
age. The gate of the MOSFET can discharge faster than
V
OUT
when shutting down the MOSFET with a large
C
LOAD
.
If one of the conditions cannot be met, an external Zener
clamp shown on Figure 10a or Figure 10b can be used.
The selection of R
G
should be within the allowed LTC4210
package dissipation when discharging V
OUT
via the Zener
clamp.
Table 1. t
INITIAL
, t
CBDELAY
, t
COOLOFF
vs C
TIMER
C
TIMER
(µF) t
INITIAL
(ms) t
CBDELAY
(ms) t
COOLOFF
(ms)
0.033 9.0 0.7 18.2
0.047 12.8 1 25.9
0.068 18.6 1.5 37.4
0.082 22.4 1.8 45.1
0.1 27.3 2.2 55
0.22 60.0 4.8 121
0.33 90.1 7.2 181.5
0.47 128.3 10.2 258.5
0.68 185.6 14.7 374
0.82 223.8 17.8 451
1 272.9 21.7 550
2.2 600.5 47.7 1210
3.3 900.7 71.5 1815
LTC4210 -1/LTC4210 -2
17
421012fa
For more information www.linear.com/LTC4210-1
APPLICATIONS INFORMATION
Figure 10. Gate Protection Zener Clamp
Figure 11. Supply Side Overvoltage Protection
+
V
CC
SENSE
LTC4210
6
3
1
2
5
C
LOAD
470µF
V
OUT
5V
4A
GND
4210 F11
4
R4
100Ω
GATE
GND
TIMER
ON
SHORT
LONG
V
IN
5V
GND
LONG
R
ON2
10k
R
ON1
20k
R
X
10Ω
R
SENSE
0.01Ω
PCB EDGE
CONNECTOR
(MALE)
Q1
Si4410DY
Z1
R
TIMER
18Ω
R
G
100Ω
C
TIMER
0.22µF
C
X
0.1µF
C
C
10nF
Z2
D1
1N4148
BACKPLANE
CONNECTOR
(FEMALE)
R
B
10k
Z1: SMAJ10A Z2: BZX84C6V2
D1*
Q1
GATE
(10a) (10b)
R
SENSE
V
OUT
R
S
200Ω
V
CC
D2*D1*
Q1
GATE
R
SENSE
V
OUT
R
S
200Ω
*USER SELECTED VOLTAGE CLAMP
(A LOW BIAS CURRENT ZENER DIODE
IS RECOMMENDED)
1N4688 (5V)
1N4692 (7V)
1N4695 (9V)
1N4702 (15V)
V
CC
LTC4210 -1/LTC4210 -2
18
421012fa
For more information www.linear.com/LTC4210-1
APPLICATIONS INFORMATION
capacitors, since controlling the surge current to bypass
capacitors at plug-in is the primary motivation for the hot
swap controller. Although wire harness, backplane and PCB
trace inductances are usually small, these can create large
spikes when large currents are suddenly drawn, cut-off or
limited. This can cause detrimental damage to board com
-
ponents unless measures are taken. Abrupt intervention
can prevent subsequent damage caused by a catastrophic
fault but it does cause a large supply transient. The energy
stored in the lead/trace inductance is easily controlled with
snubbers and/or transient voltage suppressors. Even when
ferrite beads are used for electromagnetic interference
(EMI) control, the low saturating current of ferrite will not
pose a major problem if the transient voltage suppressors
with adequate ratings are used. The transient associated
with the GATE turn off can be controlled with a snubber
and/or transient voltage suppressor. Snubbers such as RC
networks are effective especially at low voltage supplies.
The choice of RC is usually determined experimentally.
The value of the snubber capacitor is usually chosen
between 10 to 100 times the MOSFET C
OSS
. The value
of the snubber resistor is typically between to 100Ω.
When the supply exceeds 7V or EMI beads exist in the
wire harness, a transient voltage suppressor and snubber
are recommended to clip off large spikes and reduce the
ringing. For supply voltages of 6V or below, a snubber
network should be sufficient to protect against transient
voltages. In many cases, a simple short-circuit test can
be performed to determine the need of the transient volt
-
age suppressor.
OVERVOLTAGE DETECTION USING THE TIMER PIN
Figure 11 shows a supply side overvoltage detection
circuit. A Zener diode, a diode and COMP2 threshold sets
the overvoltage threshold. Resistor RB biases the Zener
diode voltage. Diode D1 blocks forward current in the
Zener during start-up or output short-circuit. R
TIMER
with
C
TIMER
sets the overload noise filter.
A MOSFET with a V
GS
absolute maximum rating of ±20V
meets the two criteria for all the LTC4210 applications
ranges from 2.7V to 16.5V. Typically most 10V gate rated
MOSFETs have V
GS
absolute maximum ratings of ±20V or
greater, so no external V
GS
Zener clamp is needed. There
are 4.5V gate rated MOSFETs with V
GS
absolute maximum
ratings of ±20V.
In addition to the MOSFET gate drive rating and V
GS
abso-
lute maximum rating, other criteria such as V
BDSS
, I
D(MAX)
,
R
DS(ON)
, P
D
, θ
JA
, T
J(MAX)
and maximum safe operating
area should also be carefully reviewed. V
BDSS
should
exceed the maximum supply voltage inclusive of spikes
and ringing. I
D(MAX)
should be greater than the current
limit, I
LIMIT
. R
DS(ON)
determines the MOSFET V
DS
which
together with V
CB
yields an error in the V
OUT
voltage. At
2.7V supply voltage, the total of V
DS
+ V
CB
of 0.1V yields
3.7% V
OUT
error.
The maximum power dissipated in the MOSFET is
I
LIMIT
2
R
DS(ON)
and this should be less than the maximum
power dissipation, P
D
allowed in that package. Given power
dissipation, the MOSFET junction temperature, T
J
can be
computed from the operating temperature (T
A
) and the
MOSFET package thermal resistance (θ
JA
). The operating
T
J
should be less than the T
J(MAX)
specification.
Next review the short-circuit condition under maximum
supply V
IN(MAX)
conditions and maximum current limit,
I
LIMIT(MAX)
during the circuit breaker time-out interval
of t
CBDELAY
with the maximum safe operating area of
the MOSFET. The operation during output short-circuit
conditions must be well within the manufacturers recom
-
mended safe operating region with sufficient margin. To
ensure a reliable design, fault tests should be evaluated
in the laboratory.
V
IN
TRANSIENT PROTECTION
Unlike most circuits, hot swap controllers typically are not
allowed the good engineering practice of supply bypass

LTC4210-2IS6#TRMPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Hot Swap Voltage Controllers Hot Swap Cntr in 6-Lead SOT-23 Package
Lifecycle:
New from this manufacturer.
Delivery:
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