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IDT72V36102L15PF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
7
COMMERCIAL TEMPERATURE RANGE
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO
TM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT72V3682/72V3692/72V36102 with
CLKA and CLKB set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were
disconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of these device's
inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
PT = VCC x ICC(f) + Σ(CL x VCC
2
X fo)
N
where:
N = number of outputs = 36
CL = output capacitance load
fo = switching frequency of an output
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
010203040506070
0
10
20
30
40
50
60
fS
⎯
Clock Frequency
⎯
MHz
ICC(f) Supply Current mA
fdata = 1/2 fS
TA = 25°C
C
L = 0 pF
4679 drw 04
70
90
80
100
80
90
100
VCC = 3.3V
V
CC = 3.6V
V
CC = 3.0V
8
COMMERCIAL TEMPERATURE RANGE
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO
TM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
IDT72V3682L10 IDT72V3682L15
IDT72V3692L10 IDT72V3692L15
IDT72V36102L10 IDT72V36102L15
Symbol Parameter Min. Max. Min. Max. Unit
fS Clock Frequency, CLKA or CLKB — 100 — 66.7 MHz
tCLK Clock Cycle Time, CLKA or CLKB 10 — 15 — ns
t
CLKH Pulse Duration, CLKA or CLKB HIGH 4.5 — 6 — ns
t
CLKL Pulse Duration, CLKA and CLKB LOW 4.5 — 6 — ns
tDS Setup Time, A0-A35 before CLKA↑ and B0-B35 3 — 4 — ns
before CLKB↑
t
ENS1 Setup Time, CSA and W/RA, before 4 — 4.5 — ns
CLKA↑; CSB, and W/RB before CLKB↑
tENS2 Setup Time, ENA and MBA, before 3 — 4.5 — ns
CLKA↑; ENB, and MBB before CLKB↑
tRSTS Setup Time, RST1 or RST2 LOW before CLKA↑ 5— 5—ns
or CLKB↑
(1)
tFSS
Setup Time, FS0 and FS1 before RST1 and RST2 HIGH
7.5 — 7.5 — ns
tFWS Setup Time, FWFT before CLKA↑ 0— 0—ns
tDH
Hold Time, A0-A35 after CLKA
↑
and B0-B35 after CLKB
↑ 0.5 — 1 — ns
tENH Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; 0.5 — 1 — ns
CSB, W/RB, ENB, and MBB after CLKB↑
tRSTH
Hold Time, RST1 or RST2 LOW after CLKA
↑
or CLKB
↑
(1)
4— 4—ns
tFSH Hold Time, FS0 and FS1 after RST1 and RST2 HIGH 2 — 2 — ns
tSKEW1
(2)
Skew Time, between CLKA
↑
and CLKB
↑
for EFA/ORA,
7.5 — 7.5 — ns
EFB/ORB, FFA/IRA, and FFB/IRB
tSKEW2
(2,3)
Skew Time, between CLKA↑ and CLKB↑ for AEA,12—12—ns
AEB, AFA, and AFB
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2.
Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
3. Design simulated, not tested.
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
(Vcc = 3.3V ± 0.15V; TA = 0
ο
C to +70
ο
C; JEDEC JESD8-A compliant)
9
COMMERCIAL TEMPERATURE RANGE
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO
TM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30 pF
IDT72V3682L10 IDT72V3682L15
IDT72V3692L10 IDT72V3692L15
IDT72V36102L10 IDT72V36102L15
Symbol Parameter Min. Max. Min. Max. Unit
t
A Access Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B35 2 6.5 2 10 ns
tPIR
Propagation Delay Time, CLKA↑ to FFA/IRA and CLKB↑ to
2 6.5 2 8 ns
FFB/IRB
tPOR
Propagation Delay Time, CLKA↑ to EFA/ORA and CLKB↑ to
1 6.5 1 8 ns
EFB/ORB
tPAE
Propagation Delay Time, CLKA↑ to AEA and CLKB↑ to AEB
1 6.5 1 8 ns
tPAF
Propagation Delay Time, CLKA↑ to AFA and CLKB↑ to AFB
1 6.5 1 8 ns
t
PMF Propagation Delay Time, CLKA↑ to MBF1 LOW or 0 6.5 0 8 ns
MBF2 HIGH and CLKB↑ to MBF2 LOW or MBF1 HIGH
t
PMR Propagation Delay Time, CLKA↑ to B0-B35
(1)
and 2 8 2 10 ns
CLKB↑ to A0-A35
(2)
tMDV Propagation Delay Time, MBA to A0-A35 valid and 2 6.5 2 10 ns
MBB to B0-B35 Valid
tPRF Propagation Delay Time, RST1 LOW to AEB LOW, AFA 110115ns
HIGH, and MBF1 HIGH, and RST2 LOW to AEA LOW,
AFB HIGH, and MBF2 HIGH
tEN Enable Time, CSA and W/RA LOW to A0-A35 Active 2 6 2 10 ns
and CSB LOW and W/RB HIGH to B0-B35 Active
tDIS
Disable Time, CSA or W/RA HIGH to A0-A35 at high-impedance
1618ns
and CSB HIGH or W/RB LOW to B0-B35 at high-impedance
NOTES:
1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
(Vcc = 3.3V ± 0.15V; TA = 0
ο
C to +70
ο
C; JEDEC JESD8-A compliant)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

IDT72V36102L15PF

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IC FIFO 262KX18 15NS 120QFP
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