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MAX13103EETL+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
MAX13101E/MAX13102E/MAX13103E/MAX13108E
16-Channel Buffered CMOS
Logic-Level Translators
4 _______________________________________________________________________________________
TIMING CHARACTERISTICS
(V
CC
= +1.65V to +5.5V, V
L
= +1.2V to V
CC
, EN = V
L
(MAX13101E/MAX13102E/MAX13103E), MULT = V
L
or GND (MAX13108E),
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at V
CC
= +1.65V, V
L
= +1.2V, T
A
= +25°C.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
I/O V
L
_ Rise Time t
RVL
R
S
= 50Ω, C
I/OVL_
= 15pF, t
RISE
≤ 3ns,
(Figures 2a, 2b)
15 ns
I/O V
L
_ Fall Time t
FVL
R
S
= 50Ω, C
I/OVL_
= 15pF, t
FALL
≤ 3ns,
(Figures 2a, 2b)
15 ns
I/O V
CC
_ Rise Time t
RVCC
R
S
= 50Ω, C
I/OVCC_
= 50pF, t
RISE
≤ 3ns,
(Figures 1a, 1b)
15 ns
I/O V
CC
_ Fall Time t
FVCC
R
S
= 50Ω, C
I/OVCC_
= 50pF, t
FALL
≤ 3ns,
(Figures 1a, 1b)
15 ns
Propagation Delay
(Driving I/O V
L
_)
t
PVL-VCC
R
S
= 50Ω, C
I/OVCC_
= 50pF, t
RISE
≤ 3ns,
(Figures 1a, 1b)
20 ns
Propagation Delay
(Driving I/O V
CC
_)
t
PVCC-VL
R
S
= 50Ω, C
I/OVL_
= 15pF, t
RISE
≤ 3ns,
(Figures 2a, 2b)
20 ns
Channel-to-Channel Skew t
SKEW
R
S
= 50Ω, C
I/OVCC_
= 50pF, C
I/OVL_
=
15pF, t
RISE
≤ 3ns
5ns
Part-to-Part Skew
t
PPSKEW
R
S
= 50Ω, C
I/OVCC_
= 50pF, C
I/OVL_
=
15pF, t
RISE
≤ 3ns, ΔT
A
= +20°C (Notes 3, 4)
10 ns
Propagation Delay from
I/O V
L
_ to I/O V
CC
_ After EN
t
EN-VCC
C
I/OVCC_
= 50pF (Figure 3) 1 µs
Propagation Delay from
I/O V
CC
_ to I/O V
L
_ After EN
t
EN-VL
C
I/OVL_
= 15pF (Figure 4) 1 µs
Maximum Data Rate
R
SOURCE
= 50Ω, C
I/OVCC_
= 50pF,
C
I/OVL_
= 15pF, t
RISE
≤ 3ns
20
Mbps
Note 1: All units are 100% production tested at T
A
= +25°C. Limits over the operating temperature range are guaranteed by design
and not production tested.
Note 2: For normal operation, ensure that V
L
< (V
CC
+ 0.3V). During power-up, V
L
> (V
CC
+ 0.3V) does not damage the device.
Note 3: V
CC
from device 1 must equal V
CC
of device 2. V
L
from device 1 must equal V
L
of device 2.
Note 4: Guaranteed by design, not production tested.
MAX13101E/MAX13102E/MAX13103E/MAX13108E
16-Channel Buffered CMOS
Logic-Level Translators
_______________________________________________________________________________________ 5
Test Circuits/Timing Diagrams
MAX13101E
MAX13102E
MAX13103E
MAX13108E
SOURCE
R
S
6kΩ
6kΩ
ALL UNUSED I/O V
CC_
AND I/O V
L_
CONNECTED TO GND
I/O V
L_
EN/(MULT)
V
L
V
CC
I/O V
CC_
C
I/OVCC_
( ) ARE FOR THE MAX13108E
t
PHL
t
PLH
50%
90%
10%
I/O V
CC_
I/O V
L_
90%
50%
10%
90%
50%
10%
t
RISE/FALL
≤ 3ns
t
FVCC
t
PVL-VCC
= t
PHL
or t
PLH
t
RVCC
SOURCE
R
S
I/O V
L_
EN/(MULT)
V
L
V
CC
I/O V
CC_
C
I/OVL_
MAX13101E
MAX13102E
MAX13103E
MAX13108E
6kΩ
6kΩ
ALL UNUSED I/O V
CC_
AND I/O V
L_
CONNECTED TO GND
( ) ARE FOR THE MAX13108E
t
PHL
t
PLH
I/O V
L_
I/O V
CC_
90%
50%
10%
90%
50%
10%
50%
90%
10%
t
RISE/FALL
≤ 3ns
t
FVL
t
RVL
t
PVCC-VL
= t
PHL
or t
PLH
Figure 1a. Driving I/O V
L_
Figure 1b. Timing for Driving I/O V
L_
Figure 2a. Driving I/O V
CC_
Figure 2b. Timing for Driving I/O V
CC_
MAX13101E/MAX13102E/MAX13103E/MAX13108E
16-Channel Buffered CMOS
Logic-Level Translators
6 _______________________________________________________________________________________
Test Circuits/Timing Diagrams (continued)
SOURCE
I/O V
CC_
100kΩ
I/O V
L_
C
I/OVCC
V
L
EN/(MULT)
I/O V
L_
I/O V
CC_
t
EN-VCC
V
L
V
L
V
CC
0
0
V
CC
2
MAX13101E
MAX13102E
MAX13103E
MAX13108E
EN/(MULT)
( ) ARE FOR THE MAX13108E
6kΩ
6kΩ
Figure 3. Propagation Delay from I/O V
L_
to I/O V
CC_
After EN
I/O V
CC_
I/O V
L_
C
I/OVL
100kΩ
V
CC
EN/(MULT)
I/O V
L_
I/O V
CC_
t
EN-VL
V
L
V
L
V
CC
0
0
0
V
L
2
SOURCE
MAX13101E
MAX13102E
MAX13103E
MAX13108E
EN/(MULT)
( ) ARE FOR THE MAX13108E
6kΩ
6kΩ
Figure 4. Propagation Delay from I/O V
CC_
to I/O V
L_
After EN
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

MAX13103EETL+

Mfr. #:
Buy MAX13103EETL+
Manufacturer:
Maxim Integrated
Description:
Translation - Voltage Levels 16-Ch 20Mbps 5.5V Logic Level Tr
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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