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TDA7535

P1-P3P4-P6P7-P9P10-P12
TDA7535 I
2
S interface
7/12
3 I
2
S interface
Figure 3. I
2
S interface diagram
Figure 4. I
2
S timings
FSYNC
SDATA
SCK
32 * SCK
32 * SCK
20 Bits
MSB
LSB
20 Bits
MSB
LSB
Left
Right
t
sck
t
sckpl
t
sds
t
lrw-
t
sckph
t
lrw+
t
sdh
Valid
FSYNC
SDATA
SCK
Valid
t
sckft
sckr
Table 10. Timing characteristics
Timing Description Min. Max. Unit
t
sck
Clock cycle
(1)
1/(64*Fs) - 150ps
RMS
1/(64*Fs) + 150ps
RMS
ns
t
sckpl
SCK phase low 0.5*t
sck
- 1% 0.5*t
sck
+1% ns
t
sckph
SCK phase high 0.5*t
sck
- 1% 0.5*t
sck
+1% ns
t
lrw-
FSYNC switching time window before SCK falling
edge
(2)
0 0.125*t
sck
-10 ns
t
lrw+
FSYNC switching time window after SCK falling
edge
(2))
0 0.125*t
sck
-10 ns
t
sds
SDATA setup time 60 ns
t
sdh
SDATA hold time 30 ns
Obsolete Product(s) - Obsolete Product(s)
I
2
S interface TDA7535
8/12
Figure 5. Power up and reset sequence
Figure 6. Frequency response
t
sckr
SCK rise time 22 ns
t
sckf
SCK fall time 20 ns
1. SCK clock defines the Fs, being the Sample Rate. This input clock needs a jitter below ~212ps
RMS
.
2. FSYNC switches inside the time window as specified w.r.t. to falling edge of SCK.
Table 10. Timing characteristics (continued)
Timing Description Min. Max. Unit
T
RES
T
RES
Min 50ms
V
DD
RESET
D02AU141
8
Obsolete Product(s) - Obsolete Product(s)
TDA7535 Application circuit
9/12
4 Application circuit
Figure 7. Application circuit
10μH
bead inductor
SDATA
7
TP1
TP7
J4
BNC
J3
BNC
TP8
2
OUTSR
SCK
TP2
3
FSYNC
I
2
S
TP3
13
GND_DIG
5
GND_ANA
VCM
6
9
8
TP5
+3.3VANA
+3.3 VDIG
μP
R2 10K
100nF(*)
100nF(*)
C15
47μF 10V
(*)
C7
10μF
10V
10μF
10μF
SW1
C16
100nF
(*)
TP6
OUTSL
10
VDD_ANA
12
VDD_DIG
RESETN
OUTSR
OUTSL
14
D02AU1419B
U4
(*) AS CLOSE AS POSSIBLE TO THE PIN
Obsolete Product(s) - Obsolete Product(s)
P1-P3P4-P6P7-P9P10-P12

TDA7535

Mfr. #:
Buy TDA7535
Manufacturer:
STMicroelectronics
Description:
DAC 20BIT DELTA/SIGMA STER 14SOI
Lifecycle:
New from this manufacturer.
Delivery:
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