OV
CC
) where they enter the PCB with separate net-
works of ferrite beads and capacitors to their corre-
sponding grounds (AGND, OGND).
To achieve optimum performance, provide each supply
with a separate network of a 47µF tantalum capacitor in
parallel with 10µF and 1µF ceramic capacitors.
Additionally, the ADC requires each supply pin to be
bypassed with separate 0.1µF ceramic capacitors
(Figure 10). Locate these capacitors directly at the ADC
supply pins or as close as possible to the MAX1123.
Choose surface-mount capacitors, which are preferably
located on the same side as the converter, to save
space and minimize the inductance.
Multilayer boards with separated ground and power
planes produce the highest level of signal integrity.
Consider the use of a split ground plane arranged to
match the physical location of analog and digital
ground on the ADC’s package. The two ground planes
should be joined at a single point so the noisy digital
ground currents do not interfere with the analog ground
plane. A major concern with this approach are the
dynamic currents that may need to travel long dis-
tances before they are recombined at a common
source ground, resulting in large and undesirable
ground loops. Ground loops can add to digital noise by
coupling back to the analog front end of the converter,
resulting in increased spur activity and a decreased
noise performance.
Alternatively, all ground pins could share the same
ground plane, if the ground plane is sufficiently isolated
from any noisy, digital systems ground. To minimize the
effects of digital noise coupling, ground return vias can
be positioned throughout the layout to divert digital
switching currents away from the sensitive analog sec-
tions of the ADC. This does not require additional
ground splitting, but can be accomplished by placing
substantial ground connections between the analog
front end and the digital outputs.
The MAX1123 is packaged in a 68-pin QFN-EP pack-
age (package code: G6800-4), providing greater
design flexibility, increased thermal efficiency, and opti-
mized AC performance of the ADC. The EP must be
soldered down to AGND.
In this package, the data converter die is attached to
an EP lead frame with the back of this frame exposed
at the package bottom surface, facing the PCB side of
the package. This allows a solid attachment of the
package to the PCB with standard infrared (IR) flow sol-
dering techniques.
Note that thermal efficiency is not the key factor, since
the MAX1123 features low-power operation. The
exposed pad is the key element to ensure a solid
ground connection between the DAC and the PCB’s
analog ground layer.
Considerable care must be taken, when routing the
digital output traces for a high-speed, high-resolution
data converter. It is essential to keep trace lengths at a
minimum and place minimal capacitive loading—less
than 5pF—on any digital trace to prevent coupling to
sensitive analog sections of the ADC. It is recommend-
ed to run the LVDS output traces as differential lines
with 100Ω characteristic impedance from the ADC to
the LVDS load device.
MAX1123
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
______________________________________________________________________________________ 15
