MAX7321AEE+ Datasheet MAX7321ATE+T, MAX7321AEE+, MAX7321ATE+ | P7-P9

RST

Input

The RST input voids any I

C transaction involving the

MAX7321, forcing the MAX7321 into the I

C STOP con-

dition. A reset does not affect the interrupt output (INT).

Standby Mode

When the serial interface is idle, the MAX7321 automat-

ically enters standby mode, drawing minimal supply

current.

Slave Address, Power-Up Default Logic

Levels, and Input Pullup Selection

Address inputs AD0 and AD2 determine the MAX7321

slave address, set the power-up I/O state for the ports,

and select which inputs have pullup resistors. Internal

pullups and power-up default states are set in groups

of four (Table 3). The MAX7319, MAX7321, MAX7322,

and MAX7323 use a different range of slave addresses

(110xxxx) than the MAX7320 (101xxxx) (Table 2).

The MAX7321 slave address is determined on each I

transmission, regardless of whether the transmission is

actually addressing the MAX7321. The MAX7321 distin-

guishes whether address inputs AD2 and AD0 are con-

nected to SDA or SCL instead of fixed logic levels V+ or

GND during this transmission. This means that the

MAX7321 slave address can be configured dynamical-

ly in the application without cycling the device supply.

On initial power-up, the MAX7321 cannot decode

address inputs AD0 and AD2 fully until the first I

transmission. AD0 and AD2 initially appear to be con-

nected to V+ or GND. This is important because the

address selection is used to determine the power-up

logic state and whether pullups are enabled. However,

at power-up, the I

C SDA and SCL bus interface lines

are high impedance at the pins of every device (master

or slave) connected to the bus, including the MAX7321.

This is guaranteed as part of the I

C specification.

Therefore, address inputs AD2 and AD0 that are con-

nected to SDA or SCL normally appear at power-up to

be connected to V+. The power-up logic uses AD0 to

select the power-up state and whether pullups are

enabled for ports P3–P0, and AD2 for ports P7–P4. The

rule is that a logic-high, SDA, or SCL connection

selects the pullups and sets the default logic state to

high. A logic-low deselects the pullups and sets the

default logic state to low (Table 3). The port configura-

tion is correct on power-up for a standard I

C configu-

ration, where SDA or SCL are pulled up to V+ by the

external I

C pullup resistors.

MAX7321

C Port Expander with 8 Open-Drain I/Os

_______________________________________________________________________________________ 7

PART

C SLAVE

ADDRESS

INPUTS

INTERRUPT

MASK

OPEN-

DRAIN

OUTPUTS

PUSH-

PULL

OUTPUTS

C DATA WRITE I

C DATA READ

MAX7319 110xxxx 8 Yes — —

<I7–I0 interrupt

mask>

<I7–I0 port inputs>

<I7–I0 transition flags>

MAX7320 101xxxx — — — 8

<O7–O0 port

outputs>

<O7-O0 port inputs>

MAX7321 110xxxx Up to 8 — Up to 8 —

<P7–P0 port

outputs>

<P7–P0 port inputs>

<P7–P0 transition flags>

MAX7322 110xxxx 4 Yes — 4

<O7, O6 outputs,

I5–I2 interrupt

mask, O1, O0

outputs>

<O7, O6, I5–I2, O1, O0 port

inputs>

<0, 0, I5–I2 transition flags,

0, 0>

MAX7323 110xxxx Up to 4 — Up to 4 4 <port outputs>

<O7, O6, P5–P2, O1, O0 port

inputs>

<0, 0, P5–P2 transition flags,

0, 0>

MAX7328 0100xxx Up to 8 — Up to 8 —

<P7–P0 port

outputs>

<P7–P0 port inputs>

MAX7329 0111xxx Up to 8 — Up to 8 —

<P7–P0 port

outputs>

<P7–P0 port inputs>

Table 2. Read and Write Access to Eight-Port Expander Family

MAX7321

There are circumstances where the assumption that

SDA = SCL = V+ on power-up is not true—for example,

in applications in which there is legitimate bus activity

during power-up. Also, if SDA and SCL are terminated

with pullup resistors to a different supply voltage than

the MAX7321’s supply voltage, and if that pullup supply

rises later than the MAX7321’s supply, then SDA or

SCL may appear at power-up to be connected to GND.

In such applications, use the four address combina-

tions that are selected by connecting address inputs

AD2 and AD0 to V+ or GND (shown in bold in Table 3).

These selections are guaranteed to be correct at

power-up, independent of SDA and SCL behavior. If

one of the other 12 address combinations is used, an

unexpected combination of pullups might be asserted

until the first I

C transmission (to any device, not neces-

sarily the MAX7321) is put on the bus, and an unex-

pected combination of ports may initialize as logic-low

outputs instead of inputs or logic-high outputs.

Port Inputs

I/O port inputs switch at the CMOS-logic levels as

determined by the expander’s supply voltage, and are

overvoltage tolerant to +6V, independent of the

expander’s supply voltage.

I/O Port Input Transition Detection

All I/O ports configured as inputs are monitored for

changes since the expander was last accessed

through the serial interface. The state of the input ports

is stored in an internal “snapshot” register for transition

monitoring. The snapshot is continuously compared

with the actual input conditions, and if a change is

detected for any port, INT is asserted to signal a state

change. An internal transition flag is set for that port.

The input is sampled (internally latched into the snap-

shot register) and the old transition flags cleared during

the I

C acknowledge of every MAX7321 read and write

access. The previous port transition flags are read

through the serial interface as the second byte of a

2-byte read sequence.

C Port Expander with 8 Open-Drain I/Os

8 _______________________________________________________________________________________

PIN CONNECTION DEVICE ADDRESS 40kΩ INPUT PULLUP ENABLES

AD2 AD0 A6 A5 A4 A3 A2 A1 A0 I7 I6 I5 I4 I3 I2 I1 I0

SCL GND 1100000YYYY————

SCL V+ 1100001YYYYYYYY

SCL SCL 1 1 0 0 0 1 0 Y Y Y Y Y Y Y Y

SCL SDA 1 1 0 0 0 1 1 Y Y Y Y Y Y Y Y

SDA GND 1100100YYYY————

SDA V+ 1100101YYYYYYYY

SDA SCL 1 1 0 0 1 1 0 Y Y Y Y Y Y Y Y

SDA SDA 1 1 0 0 1 1 1 Y Y Y Y Y Y Y Y

GND GND 1101000————————

GND V+ 1101001————YYYY

GND SCL 1101010————YYYY

GND SDA 1101011————YYYY

V+ GND 1101100YYYY————

V+ V+ 1101101YYYYYYYY

V+ SCL 1101110YYYYYYYY

V+ SDA 1101111YYYYYYYY

Table 3. MAX7321 Address Map

Serial Interface

Serial Addressing

The MAX7321 operates as a slave that sends and

receives data through an I

C interface. The interface

uses a serial data line (SDA) and a serial clock line (SCL)

to achieve bidirectional communication between mas-

ter(s) and slave(s). The master initiates all data transfers

to and from the MAX7321 and generates the SCL clock

that synchronizes the data transfer (Figure 1).

SDA operates as both an input and an open-drain out-

put. A pullup resistor, typically 4.7kΩ, is required on

SDA. SCL operates only as an input. A pullup resistor,

typically 4.7kΩ, is required on SCL if there are multiple

masters on the 2-wire interface, or if the master in a sin-

gle-master system has an open-drain SCL output.

Each transmission consists of a START condition sent

by a master, followed by the MAX7321’s 7-bit slave

address plus R/W bit, 1 or more data bytes, and finally

a STOP condition (Figure 2).

START and STOP Conditions

Both SCL and SDA remain high when the interface is

not busy. A master signals the beginning of a transmis-

sion with a START (S) condition by transitioning SDA

from high to low while SCL is high. When the master

has finished communicating with the slave, the master

issues a STOP (P) condition by transitioning SDA from

low to high while SCL is high. The bus is then free for

another transmission (Figure 2).

Bit Transfer

One data bit is transferred during each clock pulse.

The data on SDA must remain stable while SCL is high

(Figure 3).

Acknowledge

The acknowledge bit is a clocked 9th bit the recipient

uses to acknowledge receipt of each byte of data

(Figure 4). Each byte transferred effectively requires 9

bits. The master generates the 9th clock pulse, and the

recipient pulls down SDA during the acknowledge

clock pulse, such that the SDA line is stable low during

the high period of the clock pulse. When the master is

transmitting to the MAX7321, the MAX7321 generates

the acknowledge bit because the device is the recipi-

ent. When the MAX7321 is transmitting to the master,

the master generates the acknowledge bit because the

master is the recipient.

Slave Address

The MAX7321 has a 7-bit-long slave address (Figure

5). The eighth bit following the 7-bit slave address is

the R/W bit. It is low for a write command, and high for

a read command.

The first (A6), second (A5), and third (A4) bits of the

MAX7321 slave address are always 1, 1, and 0.

Connect AD2 and AD0 to GND, V+

SDA, or SCL to

select slave address bits A3, A2, A1, and A0. The

MAX7321 has 16 possible slave addresses (Table 3),

allowing up to 16 MAX7321 devices on an I

C bus.

MAX7321

C Port Expander with 8 Open-Drain I/Os

_______________________________________________________________________________________ 9

SCL

SDA

BUF

START

CONDITION

STOP

CONDITION

REPEATED START CONDITION

START CONDITION

SU,STO

HD,STA

SU,STA

HD,DAT

SU,DAT

LOW

HIGH

HD,STA

Figure 1. 2-Wire Serial Interface Timing Details

SDA

SCL

START

CONDITION

STOP

CONDITION

Figure 2. START and STOP Conditions

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

MAX7321AEE+

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Interface - I/O Expanders I2C Port Expander w/8 Open-Drain I/Os

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