10
LT1358/LT1359
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Layout and Passive Components
The LT1358/LT1359 amplifiers are easy to use and toler-
ant of less than ideal layouts. For maximum performance
(for example, fast 0.01% settling) use a ground plane,
short lead lengths, and RF-quality bypass capacitors
(0.01µF to 0.1µF). For high drive current applications use
low ESR bypass capacitors (1µF to 10µF tantalum).
The parallel combination of the feedback resistor and gain
setting resistor on the inverting input combine with the
input capacitance to form a pole which can cause peaking
or oscillations. If feedback resistors greater than 5k are
used, a parallel capacitor of value
C
F
> R
G
x C
IN
/ R
F
should be used to cancel the input pole and optimize
dynamic performance. For unity-gain applications where
a large feedback resistor is used, C
F
should be greater than
or equal to C
IN
.
Capacitive Loading
The LT1358/LT1359 are stable with any capacitive load.
As the capacitive load increases, both the bandwidth and
phase margin decrease so there will be peaking in the
frequency domain and in the transient response. Coaxial
cable can be driven directly, but for best pulse fidelity a
resistor of value equal to the characteristic impedance of
the cable (i.e., 75) should be placed in series with the
output. The other end of the cable should be terminated
with the same value resistor to ground.
Input Considerations
Each of the LT1358/LT1359 inputs is the base of an NPN
and a PNP transistor whose base currents are of opposite
polarity and provide first-order bias current cancellation.
Because of variation in the matching of NPN and PNP beta,
the polarity of the input bias current can be positive or
negative. The offset current does not depend on NPN/PNP
beta matching and is well controlled. The use of balanced
source resistance at each input is recommended for
applications where DC accuracy must be maximized.
The inputs can withstand transient differential input volt-
ages up to 10V without damage and need no clamping or
source resistance for protection. Differential inputs, how-
ever, generate large supply currents (tens of mA) as
required for high slew rates. If the device is used with
sustained differential inputs, the average supply current
will increase, excessive power dissipation will result and
the part may be damaged. The part should not be used
as a comparator, peak detector or other open-loop
application with large, sustained differential inputs.
Under normal, closed-loop operation, an increase of power
dissipation is only noticeable in applications with large
slewing outputs and is proportional to the magnitude of
the differential input voltage and the percent of the time
that the inputs are apart. Measure the average supply
current for the application in order to calculate the power
dissipation.
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LT1358/LT1359
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Circuit Operation
The LT1358/LT1359 circuit topology is a true voltage
feedback amplifier that has the slewing behavior of a
current feedback amplifier. The operation of the circuit can
be understood by referring to the simplified schematic.
The inputs are buffered by complementary NPN and PNP
emitter followers which drive a 500 resistor. The input
voltage appears across the resistor generating currents
which are mirrored into the high impedance node. Comple-
mentary followers form an output stage which buffers the
gain node from the load. The bandwidth is set by the input
resistor and the capacitance on the high impedance node.
The slew rate is determined by the current available to
charge the gain node capacitance. This current is the
differential input voltage divided by R1, so the slew rate is
proportional to the input. Highest slew rates are therefore
seen in the lowest gain configurations. For example, a 10V
output step in a gain of 10 has only a 1V input step,
whereas the same output step in unity gain has a 10 times
greater input step. The curve of Slew Rate vs Input Level
illustrates this relationship. The LT1358/LT1359 are tested
for slew rate in a gain of –2 so higher slew rates can be
expected in gains of 1 and –1, and lower slew rates in
higher gain configurations.
The RC network across the output stage is bootstrapped
when the amplifier is driving a light or moderate load and
has no effect under normal operation. When driving a
capacitive load (or a low value resistive load) the network
is incompletely bootstrapped and adds to the compensa-
tion at the high impedance node. The added capacitance
slows down the amplifier which improves the phase
margin by moving the unity-gain frequency away from the
pole formed by the output impedance and the capacitive
load. The zero created by the RC combination adds phase
to ensure that even for very large load capacitances, the
total phase lag can never exceed 180 degrees (zero phase
margin) and the amplifier remains stable.
Power Dissipation
The LT1358/LT1359 combine high speed and large output
drive in small packages. Because of the wide supply
voltage range, it is possible to exceed the maximum
junction temperature under certain conditions. Maximum
junction temperature (T
J
) is calculated from the ambient
temperature (T
A
) and power dissipation (P
D
) as follows:
LT1358N8: T
J
= T
A
+ (P
D
x 130°C/W)
LT1358S8: T
J
= T
A
+ (P
D
x 190°C/W)
LT1359N: T
J
= T
A
+ (P
D
x 110°C/W)
LT1359S: T
J
= T
A
+ (P
D
x 150°C/W)
LT1359S14: T
J
= T
A
+ (P
D
x 160°C/W)
Worst case power dissipation occurs at the maximum
supply current and when the output voltage is at 1/2 of
either supply voltage (or the maximum swing if less than
1/2 supply voltage). For each amplifier P
DMAX
is:
P
DMAX
= (V
+
– V
)(I
SMAX
) + (V
+
/2)
2
/R
L
Example: LT1358 in S8 at 70°C, V
S
= ±15V, R
L
= 500
P
DMAX
= (30V)(2.9mA) + (7.5V)
2
/500 = 200mW
T
JMAX
= 70°C + (2 x 200mW)(190°C/W) = 146°C
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LT1358/LT1359
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135859 SS01
OUT
+IN
–IN
V
+
V
R1
500
C
C
R
C
C
SCHE ATIC
WW
SI PLIFIED

LT1358IS8#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Operational Amplifiers - Op Amps Dual 2mA 25MHz 600V/uSec OA
Lifecycle:
New from this manufacturer.
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