Data Sheet ADuM140D/ADuM140E
Rev. 0 | Page 15 of 18
APPLICATIONS INFORMATION
OVERVIEW
The ADuM140D/ADuM140E use a high frequency carrier to
transmit data across the isolation barrier using iCoupler chip
scale transformer coils separated by layers of polyimide isolation.
Using an on-off keying (OOK) technique and the differential
architecture shown in Figure 11 and Figure 12, the ADuM140D/
ADuM140E have very low propagation delay and high speed.
Internal regulators and input/output design techniques allow
logic and supply voltages over a wide range from 1.7 V to 5.5 V,
offering voltage translation of 1.8 V, 2.5 V, 3.3 V, and 5 V logic.
The architecture is designed for high common-mode transient
immunity and high immunity to electrical noise and magnetic
interference. Radiated emissions are minimized with a spread
spectrum OOK carrier and other techniques.
Figure 11 illustrates the waveforms for models of the ADuM140D/
ADuM140E with the condition of the fail-safe output state equal
to low, where the carrier waveform is off when the input state is
low. If the input side is off or not operating, the fail-safe output state
of low sets the output to low. For the ADuM140D/ADuM140E
with a fail-safe output state of high, Figure 12 illustrates the
conditions where the carrier waveform is off when the input
state is high. When the input side is off or not operating, the
fail-safe output state of high sets the output to high. See the
Ordering Guide for the model numbers that have the fail-safe
output state of low or the fail-safe output state of high.
PCB LAYOUT
The ADuM140D/ADuM140E digital isolators require no external
interface circuitry for the logic interfaces. Power supply bypassing
is strongly recommended at the input and output supply pins
(see Figure 10). Bypass capacitors are most conveniently connected
between Pin 1 and Pin 2 for V
DD1
and between Pin 15 and Pin 16
for V
DD2
. The recommended bypass capacitor value is between
0.01 μF and 0.1 μF. The total lead length between both ends of
the capacitor and the input power supply pin must not exceed
10 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9
and Pin 16 must also be considered, unless the ground pair on
each package side is connected close to the package.
V
DD1
GND
1
V
IA
V
IB
V
IC
V
ID
DISABLE
1
/N/A
NIC = NO INTERNAL CONNECTION. LEAVE THIS PIN FLOATING.
N/A = NOT APPLICABLE.
GND
1
V
DD2
GND
2
V
OA
V
OB
V
OC
V
OD
NIC/V
E2
GND
2
13119-010
Figure 10. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout such that any coupling
that does occur equally affects all pins on a given component
side. Failure to ensure this can cause voltage differentials between
pins exceeding the Absolute Maximum Ratings of the device,
thereby leading to latch-up or permanent damage.
See the AN-1109 Application Note for board layout guidelines.
TRANSMITTER
GND
1
GND
2
V
IN
V
OUT
RECEIVER
REGULATOR REGULATOR
13119-014
Figure 11. Operational Block Diagram of a Single Channel with a Low Fail-Safe Output State
TRANSMITTER
GND
1
GND
2
IN
V
OUT
RECEIVER
REGULATOR REGULATOR
13119-015
Figure 12. Operational Block Diagram of a Single Channel with a High Fail-Safe Output State
