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LT1810CS8#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
LT1809/LT1810
16
180910fa
APPLICATIONS INFORMATION
Rail-to-Rail Characteristics
The LT1809/LT1810 have an input and output signal range
that includes both negative and positive power supply.
Figure 1 depicts a simplifi ed schematic of the amplifi er.
The input stage is comprised of two differential amplifi ers,
a PNP stage Q1/Q2 and a NPN stage Q3/Q4 that are active
over different ranges of common mode input voltage. The
PNP differential pair is active for common mode voltages
between the negative supply to approximately 1.5V below
the positive supply. As the input voltage moves closer
toward the positive supply, the transistor Q5 will steer
the tail current I
1
to the current mirror Q6/Q7, activating
the NPN differential pair and causing the PNP pair to
become inactive for the rest of the input common mode
range up to the positive supply.
A pair of complementary common emitter stages
Q14/Q15 form the output stage, enabling the output to
swing from rail-to-rail. The capacitors C1 and C2 form
the local feedback loops that lower the output impedance
at high frequency. These devices are fabricated on Linear
Technology’s proprietary high speed complementary
bipolar process.
Power Dissipation
The LT1809/LT1810 amplifi ers combine high speed with
large output current in a small package, so there is a need
to ensure that the die’s junction temperature does not
exceed 150°C. The LT1809 is housed in an SO-8 package
or a 6-lead SOT-23 package and the LT1810 is in an SO-8
or 8-lead MSOP package. All packages have the V
–
sup-
ply pin fused to the lead frame to enhance the thermal
conductance when connecting to a ground plane or a large
metal trace. Metal trace and plated through-holes can be
used to spread the heat generated by the device to the
backside of the PC board. For example, on a 3/32" FR-4
board with 2oz copper, a total of 660 square millimeters
connected to Pin 4 of LT1810 in an SO-8 package (330
square millimeters on each side of the PC board) will bring
the thermal resistance, θ
JA
, to about 85°C/W. Without
extra metal trace connected to the V
–
pin to provide a heat
sink, the thermal resistance will be around 105°C/W. More
information on thermal resistance for all packages with
various metal areas connecting to the V
–
pin is provided
in Tables 1, 2 and 3 for thermal consideration.
Figure 1. LT1809 Simplifi ed Schematic Diagram
Q4
Q6
Q3
Q7
Q10
Q1
Q13 Q15
OUT
Q2
Q11
Q12
Q9
Q5 V
BIAS
I
1
D2
D1
D5
D4
D3
D6
D7
D8
ESDD2
ESDD1
+IN
–IN
ESDD3
ESDD4
V
+
V
+
Q8
R2R1
R3 R4 R5
Q14
1809 F01
I
2
C2
C
C
V
–
C1
BUFFER
AND
OUTPUT BIAS
Q17
Q16
ESDD5
SHDN
V
+
R7
100k
R6
10k
D9
V
+
V
–
V
–
V
–
V
–
ESDD6
BIAS
GENERATION
LT1809/LT1810
17
180910fa
APPLICATIONS INFORMATION
Table 1. LT1809 6-Lead SOT-23 Package
COPPER AREA
TOPSIDE (mm
2
)
BOARD AREA
(mm
2
)
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)
270 2500 135°C/W
100 2500 145°C/W
20 2500 160°C/W
0 2500 200°C/W
Device is mounted on topside.
Table 2. LT1809/LT1810 SO-8 Package
COPPER AREA
TOPSIDE
(mm
2
)
BACKSIDE
(mm
2
)
BOARD AREA
(mm
2
)
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)
1100 1100 2500 65°C/W
330 330 2500 85°C/W
35 35 2500 95°C/W
35 0 2500 100°C/W
0 0 2500 105°C/W
Device is mounted on topside.
Table 3. LT1810 8-Lead MSOP Package
COPPER AREA
TOPSIDE
(mm
2
)
BACKSIDE
(mm
2
)
BOARD AREA
(mm
2
)
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)
540 540 2500 110°C/W
100 100 2500 120°C/W
100 0 2500 130°C/W
30 0 2500 135°C/W
0 0 2500 140°C/W
Device is mounted on topside.
Junction temperature T
J
is calculated from the ambient
temperature T
A
and power dissipation P
D
as follows:
T
J
= T
A
+ (P
D
• θ
JA
)
The power dissipation in the IC is the function of the
supply voltage, output voltage and the load resistance.
For a given supply voltage, the worst-case power dis-
sipation P
D(MAX)
occurs at the maximum supply current
with the output voltage at half of either supply voltage (or
the maximum swing is less than 1/2 the supply voltage).
P
D(MAX)
is given by:
P
D(MAX)
= (V
S
• I
S(MAX)
) + (V
S
/2)
2
/R
L
Example: An LT1810 in SO-8 mounted on a 2500mm
2
area
of PC board without any extra heat spreading plane con-
nected to its V
–
pin has a thermal resistance of 105°C/W,
θ
JA
. Operating on ±5V supplies with both amplifi ers
simultaneously driving 50 loads, the worst-case power
dissipation is given by:
P
D(MAX)
= 2 • (10 • 25mA) + 2 • (2.5)
2
/50
= 0.5 + 0.250 = 0.750W
The maximum ambient temperature that the part is al-
lowed to operate is:
T
A
= T
J
– (P
D(MAX)
• 105°C/W)
= 150°C – (0.750W • 105°C/W) = 71°C
To operate the device at higher ambient temperature, con-
nect more metal area to the V
–
pin to reduce the thermal
resistance of the package as indicated in Table 2.
Input Offset Voltage
The offset voltage will change depending upon which
input stage is active and the maximum offset voltage is
guaranteed to be less than 3mV. The change of V
OS
over
the entire input common mode range (CMRR) is less than
2.5mV on a single 5V and 3V supply.
Input Bias Current
The input bias current polarity depends upon a given input
common voltage at whichever input stage is operating.
When the PNP input stage is active, the input bias cur-
rents fl ow out of the input pins and fl ow into the input pins
when the NPN input stage is activated. Because the input
offset current is less than the input bias current, matching
the source resistances at the input pin will reduce total
offset error.
Output
The LT1809/LT1810 can deliver a large output current,
so the short-circuit current limit is set around 90mA to
prevent damage to the device. Attention must be paid to
keep the junction temperature of the IC below the absolute
maximum rating of 150°C (refer to the Power Dissipation
section) when the output is continuously short-circuited.
LT1809/LT1810
18
180910fa
APPLICATIONS INFORMATION
The output of the amplifi er has reverse-biased diodes
connected to each supply. If the output is forced
beyond
either supply, unlimited current will fl ow through these
diodes. If the current is transient and limited to several
hundred milliamps, no damage to the device will occur.
Overdrive Protection
When the input voltage exceeds the power supplies, two
pairs of crossing diodes, D1 to D4, will prevent the out-
put from reversing polarity. If the input voltage exceeds
either power supply by 700mV, diodes D1/D2 or D3/D4
will turn on, keeping the output at the proper polarity.
For the phase reversal protection to perform properly,
the input current must be limited to less than 5mA. If
the amplifi er is severely overdriven, an external resistor
should be used to limit the overdrive current.
The LT1809/LT1810’s input stages are also protected
against differential input voltages of 1.4V or higher by
back-to-back diodes, D5/D8, that prevent the emitter-
base breakdown of the input transistors. The current in
these diodes should be limited to less than 10mA when
they are active. The worst-case differential input voltage
usually occurs when the input is driven while the output
is shorted to ground in a unity-gain confi guration. In ad-
dition, the amplifi er is protected against ESD strikes up
to 3kV on all pins by a pair of protection diodes on each
pin that are connected to the power supplies as shown
in Figure 1.
Capacitive Load
The LT1809/LT1810 is optimized for high bandwidth and
low distortion applications. It can drive a capacitive load
about 20pF in a unity-gain confi guration and more with
higher gain. When driving a larger capacitive load, a resistor
of 10 to 50 should be connected between the output
and the capacitive load to avoid ringing or oscillation. The
feedback should still be taken from the output so that the
resistor will isolate the capacitive load to ensure stability.
Graphs on capacitive loads indicate the transient response
of the amplifi er when driving capacitive load with a speci-
fi ed series resistor.
Feedback Components
When feedback resistors are used to set up gain, care must
be taken to ensure that the pole formed by the feedback
resistors and the total capacitance at the inverting input
does not degrade stability. For instance, the LT1809 in a
noninverting gain of 2, set up with two 1k resistors and a
capacitance of 3pF (device plus PC board), will probably
ring in transient response. The pole that is formed at
106MHz will reduce phase margin by 34 degrees when the
crossover frequency of the amplifi er is around 70MHz. A
capacitor of 3pF or higher connected across the feedback
resistor will eliminate any ringing or oscillation.
SHDN Pin
The LT1809 has a SHDN pin to reduce the supply current
to less than 1.25mA. When the SHDN pin is pulled low,
it will generate a signal to power down the device. If the
pin is left unconnected, an internal pull-up resistor of 10k
will keep the part fully operating as shown in Figure 1. The
output will be high impedance during shutdown, and the
turn-on and turn-off time is less than 100ns. Because the
inputs are protected by a pair of back-to-back diodes, the
input signal will feed through to the output during shut-
down mode if the amplitude of signal between the inputs
is larger than 1.4V.
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LT1810CS8#PBF

Mfr. #:
Buy LT1810CS8#PBF
Manufacturer:
Analog Devices Inc.
Description:
High Speed Operational Amplifiers 2x 180MHz, 350V/ s R2R In & Out L Dist
Lifecycle:
New from this manufacturer.
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