6.42
IDT70V26S/L
High-Speed 16K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
2
Description
The IDT70V26 is a high-speed 16K x 16 Dual-Port Static RAM. The
IDT70V26 is designed to be used as a stand-alone 256K-bit Dual-Port
RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-
more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM
approach in 32-bit or wider memory system applications results in full-
speed, error-free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 300mW of power.
The IDT70V26 is packaged in a ceramic 84-pin PGA and
84-Pin PLCC.
Pin Configurations
(1,2,3)
NOTES:
1. All V
DD pins must be connected to power supply.
2. All V
SS pins must be connected to ground supply.
3. Package body is approximately 1.15 in x 1.15 in x .17 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
2945 drw 02
14
15
16
17
18
19
20
INDEX
21
22
23
24
11109876543218483
33 34 35 36 37 38 39 40 41 42 43 44 45
V
DD
V
SS
I/O
8L
A
8L
13
12
25
26
27
28
29
30
31
32
46 47 48 49 50 51 52 53
72
71
70
69
68
67
66
65
64
63
62
73
74
61
60
59
58
57
56
55
54
82 81 80 79 78 77 76 75
V
SS
BUSY
L
V
SS
IDT70V26J
J84-1
(4)
84-Pin PLCC
Top View
(5)
A
0L
M/S
A
0R
I/O
9L
/O
10L
/O
11L
/O
12L
/O
13L
/O
14L
/O
15L
I/O
0R
I/O
1R
I/O
2R
V
DD
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
7R
I/O
8R
A
7L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
BUSY
R
A
1R
A
3R
A
4R
A
5R
A
6R
A
7R
A
2R
I
/
O
7
L
I
/
O
6
L
I
/
O
5
L
I
/
O
4
L
I
/
O
3
L
I
/
O
2
L
V
D
D
R
/
W
L
S
E
M
L
C
E
L
U
B
L
L
B
L
A
1
2
L
V
S
S
I
/
O
1
L
I
/
O
0
L
A
1
1
L
A
1
0
L
A
9
L
O
E
L
I
/
O
9
R
/
O
1
0
R
/
O
1
1
R
/
O
1
2
R
/
O
1
3
R
/
O
1
4
R
V
S
S
/
O
1
5
R
V
S
S
A
1
2
R
A
1
1
R
A
1
0
R
A
9
R
A
8
R
O
E
R
R
/
W
R
S
E
M
R
C
E
R
U
B
R
L
B
R
A
1
3
R
A
1
3
L
,
07/21/03
