OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

70V26S55G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
6.42
IDT70V26S/L
High-Speed 16K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
10
Timing Waveform of Semaphore Read after Write Timing, Either Side
(1)
NOTES:
1. D
OR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH.
2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W"
A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If t
SPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
Timing Waveform of Semaphore Write Contention
(1,3,4)
NOTES:
1. CE = V
IH or UB & LB = VIH for the duration of the above timing (both write and read cycle).
2. "DATA
OUT VALID' represents all I/O's (I/O0-I/O15) equal to the semaphore value.
SEM
2945 drw 10
t
AW
t
EW
t
SOP
I/O
0
VALID ADDRESS
t
SAA
R/W
t
WR
t
OH
t
ACE
VALID ADDRESS
DATA
IN
VALID
DATA
OUT
t
DW
t
WP
t
DH
t
AS
t
SWRD
t
AOE
Read CycleWrite Cycle
A
0
-A
2
OE
VALID
(2)
,
SEM
"A"
2945 drw 11
t
SPS
MATCH
R/W
"A"
MATCH
A
0"A"
-A
2"A"
SIDE
"A"
(2)
SEM
"B"
R/W
"B"
A
0"B"
-A
2"B"
SIDE
(2)
"B"
,
6.42
IDT70V26S/L
High-Speed 16K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
11
2945 drw 12
t
DW
t
APS
ADDR
"A"
t
WC
DATA
OUT "B"
MATCH
t
WP
R/W
"A"
DATA
IN "A"
ADDR
"B"
t
DH
VALID
(1)
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD
(3)
t
WDD
t
BAA
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(6)
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = V
IH)".
2. To ensure that the earlier of the two ports wins.
3. t
BDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part number indicates power rating (S or L).
Timing Waveform of Write with Port-to-Port Read and BUSY
(2,4,5)
NOTES:
1. To ensure that the earlier of the two ports wins. t
APS is ignored for M/S = VIL (SLAVE).
2. CE
L = CER = VIL
3. OE = VIL for the reading port.
4. If M/S = V
IL (SLAVE), then BUSY is an input (BUSY"A" = VIH and BUSY"B" = "don't care", for this example).
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
70V26X25
Com'l
& Ind
70V26X35
Com'l Only
70V26X55
Com'l Only
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
BUSY TIMING (M/S = V
IH
)
t
BAA
BUSY Access Time from Address Match
____
25
____
35
____
45 ns
t
BDA
BUSY Disable Time from Address Not Match
____
25
____
35
____
45 ns
t
BAC
BUSY Access Time from Chip Enable Low
____
25
____
35
____
45 ns
t
BDC
BUSY Disable Time from Chip Enable High
____
25
____
35
____
45 ns
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3)
____
35
____
40
____
50 ns
t
WH
Write Hold After BUSY
(5)
20
____
25
____
25
____
ns
BUSY INPUT TIMING (M/S = VIL)
t
WB
BUSY Input to Write
(4)
0
____
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5)
20
____
25
____
25
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1)
____
55
____
65
____
85 ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
50
____
60
____
80 ns
2945 tbl 13
6.42
IDT70V26S/L
High-Speed 16K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
12
Timing Waveform of Write with BUSY
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If t
APS is not satisfied, the BUSY signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
Waveform of BUSY Arbitration Controlled by CE Timing
(1)
NOTES:
1. t
WH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W
"B", until BUSY"B" goes HIGH.
Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing
(1)
2945 drw 13
R/W
"A"
BUSY
"B"
t
WP
t
WB
R/W
"B"
t
WH
(1)
(2)
,
2945 drw 14
ADDR
"A"
and
"B"
ADDRESSES MATCH
CE
"A"
CE
"B"
BUSY
"B"
t
APS
t
BAC
t
BDC
(2)
2945 drw 15
ADDR
"A"
ADDRESS "N"
ADDR
"B"
BUSY
"B"
t
APS
t
BAA
t
BDA
(2)
MATCHING ADDRESS "N"
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

70V26S55G

Mfr. #:
Buy 70V26S55G
Manufacturer:
IDT
Description:
SRAM 16Kx16 3.3V DUAL- PORT RAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet