LTC3706EGN#PBF Datasheet LTC3706EGN#TRPBF, LTC3706IGN#TRPBF, LTC3706EGN#PBF | P10-P12

LTC3706

3706fd

OPERATION

values using the SLP pin as shown in Table 1. Note that

the amount of slope compensation doubles when the duty

cycle exceeds 50%.

Table 1

SLP PIN SLOPE (D < 0.5) SLOPE (D > 0.5)

GND 0.05 • I

SMAX

• f

OSC

0.1 • I

SMAX

• f

OSC

None None

400kΩ to GND 0.1 • I

SMAX

• f

OSC

0.2 • I

SMAX

• f

OSC

200kΩ to GND 0.15 • I

SMAX

• f

OSC

0.3 • I

SMAX

• f

OSC

100kΩ to GND 0.25 • I

SMAX

• f

OSC

0.5 • I

SMAX

• f

OSC

50kΩ to GND 0.5 • I

SMAX

• f

OSC

1.0 • I

SMAX

• f

OSC

In Table 1 above, I

SMAX

is the maximum current limit, and f

OSC

is the

switching frequency.

Current Sensing and Current Limit

For current sensing, the LTC3706 supports either a current

sense resistor or a current sense transformer. The current

sense resistor may either be placed in series with the

inductor (either high side or ground lead sensing), or

in the source of the “forward” switch. If a current sense

transformer is used, the I

–

input should be tied to V

and

the I

pin to the output of the current sense transformer.

This causes the gain of the internal current sense ampliﬁer

to be reduced by a factor of 16×, so that the maximum

current sense voltage (current limit) is increased from

78mV to 1.28V. An internal, adaptive leading edge blanking

circuit ensures clean operation for “switch” current sensing

applications.

Current limit is achieved in the LTC3706 by limiting the

maximum voltage excursion of the error signal (ITH volt-

age). Note that if slope compensation is used, the precise

value at which current limit occurs will be a function of duty

cycle (See the Typical Performance Characteristics section).

If a short circuit is applied, an independent overcurrent

comparator may be tripped. In this case, the LTC3706 will

enter a “hiccup” mode using the soft-start circuitry.

Self-Starting Architecture

When the LTC3706 is used in conjunction with the

LTC3705 primary-side controller and gate driver, a

complete self-starting isolated supply is formed. When

input voltage is ﬁrst applied in such an application, the

LTC3705 will begin switching in an “open-loop” fashion,

causing the main output to slowly ramp upwards. This

is the primary-side soft-start mode. On the secondary

side, the LTC3706 derives its operating bias voltage from

a peak-charged capacitor. This peak-charged voltage will

rise more rapidly than the main output of the converter,

so that the LTC3706 will become operational well before

the output voltage has reached its ﬁnal value.

When the LTC3706 has adequate operating voltage, it will

begin the procedure of assuming control from the primary

side. To do this, it ﬁrst measures the voltage on the power

supply’s main output and then automatically advances its

own soft-start voltage to correspond to the main output

voltage. This ensures that the output voltage increases

monotonically as the soft-start control is transferred from

primary to secondary. The LTC3706 then begins sending

PWM signals to the LTC3705 on the primary side through a

pulse transformer. When the LTC3705 has detected a stable

signal from the secondary controller, it transfers control of

the primary switches over to the LTC3706, beginning the

secondary-side soft-start mode. The LTC3706 continues

in this mode until the output voltage has ramped up to

its ﬁnal value. If for any reason, the LTC3706 either stops

sending (or initially fails to send) PWM information to the

LTC3705, the LTC3705 will detect a FAULT and initiate a

soft-start retry. (See the LTC3705 data sheet.)

Slope Compensation

Slope compensation is added at the input of the PWM

comparator to improve stability and noise margin of the

peak current control loop. The amount of slope compen-

sation can be selected from one of ﬁve preprogrammed

LTC3706

3706fd

OPERATION

Frequency Setting and Synchronization

The LTC3706 uses a single pin to set the operating

frequency, or to synchronize the internal oscillator to a

reference clock with an on-chip phase-locked loop (PLL).

The FS pin may be tied to GND, V

or have a single

resistor to GND to set the switching frequency. If a clock

signal (>2V) is detected at the FS pin, the LTC3706 will

automatically synchronize to the rising edge of the reference

clock. Table 2 summarizes the operation of the FS pin.

For synchronization between multiple LTC3706s, the

pin of one LTC3706 can be used as a master clock

reference and tied to the FS pin of the other LTC3706s.

Table 2

FS PIN SWITCHING FREQUENCY

GND 200kHz

300kHz

to GND f

OSC

(Hz) = 4R

– 200k

Reference Clock f

OSC

= f

REF

(75kHz to 500kHz)

This will cause all LTC3706’s to operate at the same fre-

quency. The phase angle of each LTC3706 that is being

synchronized can be set by using the PHASE pin. This pin

can be tied to GND, V

or have a single resistor to V

to set the phase angle (delay) of the internal oscillator

relative to the incoming sync signal on the FS pin. Any

one of ﬁve preset values can be selected as summarized

in Table 3.

Table 3

PHASE PIN LTC3706 PHASE DELAY

GND 0°

180°

226kΩ to V

60°

113kΩ to V

90°

56.2kΩ to V

120°

Soft-Start

The soft-start circuitry has ﬁve functions: 1) to provide

a shutdown, 2) to provide a smooth ramp on the output

voltage during start-up, 3) to limit the output current in

a short-circuit situation by entering a hiccup mode, 4) to

limit the maximum power dissipation in the external linear

regulator via the REGSD pin, and 5) to communicate fault

and shutdown information between multiple LTC3706s in

a PolyPhase application.

When the RUN/SS pin is pulled to GND, the chip is placed

into shutdown mode. If this pin is released, the RUN/SS

pin is initially charged with a 50µA current source. After

the RUN/SS pin gets above 0.5V, the chip is enabled. At

the instant that the LTC3706 is ﬁrst enabled, the RUN/SS

voltage is rapidly preset to a voltage that will correspond

to the main output voltage of the DC/DC converter. (See

the Self-Starting Architecture section.) After this preset

interval has completed, the normal soft-start interval begins

and the charging current is reduced to 5µA. The external

soft-start voltage is used to internally ramp up the 0.6V

reference (positive) input to the error ampliﬁer. When fully

charged, the RUN/SS voltage remains at 3V.

In the event that the sensed switch or inductor current

exceeds the overcurrent trip threshold, an internal fault

latch is tripped. This latch is also tripped when the REGSD

voltage exceeds 4V (see the Linear Regulator section).

When such a fault is detected, the LTC3706 immediately

goes to zero duty cycle and initiates a soft-start retry.

Prior to discharging the soft-start capacitor, however, the

LTC3706 ﬁrst puts a voltage pulse on the RUN/SS pin, which

trips the fault latch in any other LTC3706 that shares the

RUN/SS. This ensures an orderly shutdown of all phases

in a PolyPhase application. After the soft-start capacitor

is fully discharged, the LTC3706 attempts a restart. If the

fault is persistent, the system enters a “hiccup” mode.

LTC3706

3706fd

OPERATION

Note that in self-starting secondary-side control applica-

tions (with the LTC3705), the presence of the LT3706

bias voltage is dependent upon the regular switching of

the primary-side MOSFETs. Therefore, depending on the

details of the application circuit, the LTC3706 may lose

its bias voltage after a fault has been detected and before

completing a soft-start retry. In this case, the “hiccup-

mode” operation is actually governed by the LTC3705

soft-start circuitry. (See the LTC3705 data sheet.)

Drive Mode and Maximum Duty Cycle

Although the LTC3706 is primarily intended to be used with

the LTC3705 in 2-transistor forward applications, the MODE

pin provides the ﬂexibility to use the LTC3706 in a wide

variety of additional applications. This pin can be used to

defeat the gate drive encoding scheme, as well as change

the maximum duty cycle from its default value of 50%.

The use of the MODE pin is summarized in Table 4.

When the gate drive encoding scheme is defeated, a

standard PWM-style signal will be present at the PT

and a reference clock (in phase with the PWM signal) will

be present at the PT

–

pin. These outputs can be used in

“standalone” applications (without the LTC3705) to drive

the gates of MOSFETs in a conventional manner.

Table 4

MODE PIN

/PT

–

Mode

(MAX DUTY CYCLE)

INTENDED

APPLICATION

GND Encoded PWM

MAX

= 50%)

2-Switch Forward

with LTC3705

Encoded PWM

MAX

= 75%)

1-Switch Forward

200kΩ to GND Standard PWM

MAX

= 50%)

2-Switch Forward

Standalone

100kΩ to GND Standard PWM

MAX

= 75%)

1-Switch Forward

Standalone

Power Good/Overvoltage Protection

This circuit monitors the voltage on the FB input. The

open-drain PGOOD output will be logic high if the voltage

on the FB pin is within +17%/–7% of 0.6V. If the voltage on

the FB pin exceeds 117% of 0.6V (0.7V), an overvoltage

(OVP) is detected. For overvoltage protection, the sec-

ondary-side synchronous MOSFET is turned on while all

other MOSFETs are turned off. This protection mode is

not latched, so that the overvoltage detection is cleared if

the FB voltage falls below 115% of 0.6V (0.69V).

Linear Regulator Operation

The LTC3706 provides a linear regulator controller that

drives an external N-type pass device. This controller is used

to create a 7V DC bias from the peak-charged secondary

bias voltage (8V to 30V). Internal divider resistors are used

to establish a regulation voltage of 7V at the V

pin. An

auxiliary bias supply with a regulated voltage greater than

7V may be applied to the V

pin to bypass (bootstrap) the

linear regulator. This improves efﬁciency and also helps to

avoid overheating the linear regulator pass device.

Thermal protection for the linear regulator pass device is

also provided by means of the REGSD pin. A current is

sourced from this pin that is proportional to the voltage

across the linear regulator pass device (V

– V

). Since

the V

load current is essentially constant for a given

switching frequency and choice of power MOSFETs, the

power dissipated in the external pass device will only vary

with the voltage across it. Thus, a single resistor may be

placed between the REGSD pin and GND to develop a volt-

age that is proportional to the power in the external pass

device. An additional parallel capacitor can also be used

to account for the thermal time constant associated with

the external pass device itself. When the voltage on the

REGSD pin exceeds 4V, an overtemperature fault occurs

and the LTC3706 attempts a soft-start retry.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P22

LTC3706EGN#PBF

Mfr. #:

Buy LTC3706EGN#PBF

Manufacturer:

Analog Devices / Linear Technology

Description:

Switching Voltage Regulators Secondary-Side Sync For Cntr w/ Polyphas

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

LTC3706EGN#PBF

LTC3706EGN#PBF

Products related to this Datasheet