DS1339 I
2
C Serial Real-Time Clock
5 of 20
POWER-UP/DOWN CHARACTERISTICS
(T
A
= -40°C to +85°C) (Note 2, Figure 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Recovery at Power-Up t
REC
(Note 16) 2 ms
V
CC
Fall Time; V
PF(MAX)
to V
PF(MIN)
t
VCCF
300
µs
V
CC
Rise Time; V
PF(MIN)
to V
PF(MAX)
t
VCCR
0
µs
WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in
battery-backup mode.
Note 2: Limits at -40°C are guaranteed by design and are not production tested.
Note 3: SCL only.
Note 4:
SDA and SQW/INT.
Note 5: I
CCA
—SCL at f
SC
max, V
IL
= 0.0V, V
IH
= V
CC
, trickle charger disabled.
Note 6: Specified with the I
2
C bus inactive, V
IL
= 0.0V, V
IH
= V
CC
, trickle charger disabled.
Note 7:
V
CC
must be less than 3.63V if the 250Ω resistor is selected.
Note 8: Using recommended crystal on X1 and X2.
Note 9: Guaranteed by design; not production tested.
After this period, the first clock pulse is generated.
Note 11: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IHMIN
of the SCL signal) to bridge
the undefined region of the falling edge of SCL.
Note 12: The maximum t
HD:DAT
need only be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
Note 13:
A fast-mode device can be used in a standard-mode system, but the requirement t
SU:DAT
≥ to 250ns must then be met. This is
automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line t
R(MAX)
+
t
SU:DAT
= 1000 + 250 = 1250ns before the SCL line
is released.
Note 14: C
B
—total capacitance of one bus line in pF.
Note 15:
The parameter t
OSF
is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of 0.0V ≤
V
CC
≤ V
CCMAX
and 1.3V ≤ V
BACKUP
≤ 3.7V.
This delay applies only if the oscillator is running. If the oscillator is disabled or stopped, no power-up delay occurs.
Figure 1. Power-Up/Down Timing
