FAN5067 PRODUCT SPECIFICATION
9
REV. 1.0.1 5/2/02
Application Information
The FAN5067 Controller
The FAN5067 is a fully compliant ACPI controller IC. Used
with an ATX power supply, it generates a 3.3V or 5V Dual
and power for either SDRAM or DDR, and has a large array
of additional protection functions integrated in.
Overview of ACPI
The Advanced Configuration and Power Interface, or ACPI,
is a system for controlling the use of power in a computer. It
enables the computer manufacturer and the computer user to
determine the computer’s power usage dynamically. For
example, when the computer has been unused for a certain
time, the monitor and peripherals could be turned off, and
their states saved to memory. After a longer period, the pro-
cessor could be turned off, and the memory saved to disk. A
peripheral could then re-awaken the entire system on the
occurrence of an event, such as the arrival of a FAX on a
modem.
As shown in Figure 5, the available power inputs to the com-
puter system from the ATX power supply are +5V main, +12V
main, +3.3V main, and +5V standby. “Main” means that
these power outputs are available under full-power operation
of the system, but can be turned off in some of the power-
saving modes. “Standby” means that this power output is
always present.
The most general ACPI system requires four dual outputs:
5V dual, 3.3V dual, 3.3V SDRAM, and 2.5V dual. “Dual”
means that the power can be (but is not necessarily) present
whether the main power supplies are present or not. To
ensure the presence of these outputs, while not overloading
the standby power, they have dual inputs, from both main
power and standby. The presence or absence of the dual out-
puts is determined by the control signals to the FAN5067.
ACPI States
As shown in Table 1, there are three ACPI states that are of
primary concern to the system designer, designated S0, S3
and S5. S0 is the full-power state, the state of the computer
when it is being actively used. The other two states are sleep
states, reflecting differing levels of power-down.
S3 is a state in which the processor is powered down, but its
last state is being preserved in IC memory, which is kept on.
Since memory is fast, the computer can quickly come back
up to full operation. However, this state continues to draw
moderate power, due to the memory being kept alive.
S5 is a state in which memory is off, and the last state of the
processor has been written to the hard disk. Since the disk is
slow, the computer takes longer to come back to full operation.
However, since memory is off, this state draws minimal
power.
It is anticipated that only the following state transitions will
occur: S0
→
S3, S0
→
S5, S3
→
S5, S5
→
S0, and S3 → S0;
the transition S5 → S3 will occur only as an intermediate state
during the transition from S5 → S0. To prevent overcurrent
limit from activating, the FAN5067 blocks this transition.
For example, when PWROK = SLP_S3
= 0, and SLP_S5
transitions from 0 to 1, the FAN5067 remains in the S5 state.
See Table 2.
Dual Output
The dual output is intended to power subsystems such as the
computer’s PCI slots. A typical application that would
require the use of 3.3V dual rather than +3.3V main for a PCI
slot would be the use of a modem: if the system needs to be
able to awaken from sleep when the modem receives incom-
ing data, then that slot must be powered from dual, because
main power is off. Other slots not requiring dual power can
be configured using the control signals.
3.3V dual can be generated by two MOSFETs, one from
+3.3V main, the other from +5V standby, as shown in Figure
4. When main power is present, the MOSFET Q1 is turned on
as a switch, so that input and output are connected together.
When main power is absent, the MOSFET Q2 is controlled by
the FAN5067 as a linear regulator, generating a regulated 3.3V
from +5V standby. The MOSFET Q1 must be connected as
shown in the figures, to avoid back-feed.
The state of the MOSFETs is controlled by the SLP_S3 and
PWROK lines, as shown in Figure 3. When both SLP_S3 and
PWROK are asserted, the main switch is on, and the linear reg-
ulator is off. If either line is de-asserted, the main switch is
off and the linear regulator is on.
Q1 and Q2 as shown in Table 3 have different R
DS,on
ratings.
In a typical system, it is anticipated that full-power current
will be about 2.4A maximum, and standby current will be
about 500mA maximum. The difference in maximum cur-
rents means that Q2 can be a less expensive device than Q1.
The design of the linear regulator for a 3.3V Dual necessitates
a minimum load current of 50mA. Furthermore, in order to
guarantee stable operation, the output capacitor on the 3.3V
Dual must have a minimum ESR as shown in Figure 6. The
hatched region shows acceptable values of ESR vs. output
capacitance. Values of the output capacitor less than 47µF or
greater than 300µF are not recommended.
5V Dual can be generated by applying 5V main to the source
of Q1, and placing a resistor divider in the feedback to pin 6.
