10M16DAF256C7G Datasheet 10M08SAU324I7G, 10M25SCE144C8G, 10M16DAF256C7G | P10-P12

Feature Description

Up to 17 single-ended external inputs

for single ADC devices

One dedicated analog and 16 dual function input pins

Up to 18 single-ended external inputs

for dual ADC devices

• One dedicated analog and eight dual-function input pins in each ADC block

• Simultaneous measurement capability for dual ADC devices

On-chip temperature sensor Monitors external temperature data input with a sampling rate of up to 50

kilosamples per second

User Flash Memory

The user flash memory (UFM) block in Intel MAX 10 devices stores non-volatile

information.

UFM provides an ideal storage solution that you can access using Avalon Memory-

Mapped (Avalon-MM) slave interface protocol.

Table 9. UFM Features

Features Capacity

Endurance Counts to at least 10,000 program/erase cycles

Data retention • 20 years at 85 ºC

• 10 years at 100 ºC

Operating frequency Maximum 116 MHz for parallel interface and 7.25 MHz for

serial interface

Data length Stores data up to 32 bits length in parallel

Embedded Multipliers and Digital Signal Processing Support

Intel MAX 10 devices support up to 144 embedded multiplier blocks. Each block

supports one individual 18 × 18-bit multiplier or two individual 9 × 9-bit multipliers.

With the combination of on-chip resources and external interfaces in Intel MAX 10

devices, you can build DSP systems with high performance, low system cost, and low

power consumption.

You can use the Intel MAX 10 device on its own or as a DSP device co-processor to

improve price-to-performance ratios of DSP systems.

You can control the operation of the embedded multiplier blocks using the following

options:

• Parameterize the relevant IP cores with the Intel Quartus Prime parameter editor

• Infer the multipliers directly with VHDL or Verilog HDL

System design features provided for Intel MAX 10 devices:

Intel

MAX

10 FPGA Device Overview

M10-OVERVIEW | 2017.12.15

Intel

MAX

10 FPGA Device Overview

• DSP IP cores:

— Common DSP processing functions such as finite impulse response (FIR), fast

Fourier transform (FFT), and numerically controlled oscillator (NCO) functions

— Suites of common video and image processing functions

• Complete reference designs for end-market applications

• DSP Builder for Intel FPGAs interface tool between the Intel Quartus Prime

software and the MathWorks Simulink and MATLAB design environments

• DSP development kits

Embedded Memory Blocks

The embedded memory structure consists of M9K memory blocks columns. Each M9K

memory block of a Intel MAX 10 device provides 9 Kb of on-chip memory capable of

operating at up to 284 MHz. The embedded memory structure consists of M9K

memory blocks columns. Each M9K memory block of a Intel MAX 10 device provides

9 Kb of on-chip memory. You can cascade the memory blocks to form wider or deeper

logic structures.

You can configure the M9K memory blocks as RAM, FIFO buffers, or ROM.

The Intel MAX 10 device memory blocks are optimized for applications such as high

throughput packet processing, embedded processor program, and embedded data

storage.

Table 10. M9K Operation Modes and Port Widths

Operation Modes Port Widths

Single port ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36

Simple dual port ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36

True dual port ×1, ×2, ×4, ×8, ×9, ×16, and ×18

Clocking and PLL

Intel MAX 10 devices offer the following resources: global clock (GCLK) networks and

phase-locked loops (PLLs) with a 116-MHz built-in oscillator.

Intel MAX 10 devices support up to 20 global clock (GCLK) networks with operating

frequency up to 450 MHz. The GCLK networks have high drive strength and low skew.

The PLLs provide robust clock management and synthesis for device clock

management, external system clock management, and I/O interface clocking. The

high precision and low jitter PLLs offers the following features:

• Reduction in the number of oscillators required on the board

• Reduction in the device clock pins through multiple clock frequency synthesis from

a single reference clock source

• Frequency synthesis

• On-chip clock de-skew

• Jitter attenuation

• Dynamic phase-shift

Intel

MAX

10 FPGA Device Overview

M10-OVERVIEW | 2017.12.15

Intel

MAX

10 FPGA Device Overview

• Zero delay buffer

• Counter reconfiguration

• Bandwidth reconfiguration

• Programmable output duty cycle

• PLL cascading

• Reference clock switchover

• Driving of the ADC block

FPGA General Purpose I/O

The Intel MAX 10 I/O buffers support a range of programmable features.

These features increase the flexibility of I/O utilization and provide an alternative to

reduce the usage of external discrete components such as a pull-up resistor and a PCI

clamp diode.

External Memory Interface

Dual-supply Intel MAX 10 devices feature external memory interfaces solution that

uses the I/O elements on the right side of the devices together with the UniPHY IP.

With this solution, you can create external memory interfaces to 16-bit SDRAM

components with error correction coding (ECC).

Note: The external memory interface feature is available only for dual-supply Intel MAX 10

devices.

Table 11. External Memory Interface Performance

External Memory

Interface

(3)

I/O Standard Maximum Width Maximum Frequency (MHz)

DDR3 SDRAM SSTL-15 16 bit + 8 bit ECC 303

DDR3L SDRAM SSTL-135 16 bit + 8 bit ECC 303

DDR2 SDRAM SSTL-18 16 bit + 8 bit ECC 200

LPDDR2 SDRAM HSUL-12 16 bit without ECC 200

(4)

10M16DAF256C7G

Mfr. #:

Buy 10M16DAF256C7G

Manufacturer:

Intel / Altera

Description:

FPGA - Field Programmable Gate Array

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

10M16DAF256C7G

10M16DAF256C7G

Products related to this Datasheet