ADG528AKP-REEL

REV. B–4–
ADG528A/ADG529A
ADG528A ADG528A ADG528A
ADG529A ADG529A ADG529A
K Version B Version T Version
–40°C to –40°C to –55°C to
Parameter +25°C +85°C +25°C +85°C +25°C +125°C Units Comments
DYNAMIC CHARACTERISTICS
1
(Cont’d)
t
S
Address,
Enable Setup Time 100 100 100 ns min See Figure 1
t
H
Address,
Enable Hold Time 10 10 10 ns min See Figure 1
t
RS
Reset Pulse Width 100 100 100 ns min See Figure 2
OFF Isolation 68 68 68 dB typ V
EN
= 0.8 V, R
L
= 1 k, C
L
= 15 pF,
50 50 50 dB min V
S
= 3.5 V rms, f = 100 kHz
C
S
(OFF) 5 5 5 pF typ V
EN
= 0.8 V
C
D
(OFF)
ADG528A 22 22 22 pF typ V
EN
= 0.8 V
ADG529A 11 11 11 pF typ
Q
INJ
, Charge Injection 4 4 4 pC typ R
S
= 0 , V
S
= 0 V; Test Circuit 11
POWER SUPPLY
I
DD
0.6 0.6 0.6 mA typ V
IN
= V
INL
or V
INH
1.5 1.5 1.5 mA max
Power Dissipation 11 10 10 mW typ
25 25 25 mW max
NOTE
1
Sample tested at +25°C to ensure compliance.
Specifications subject to change without notice.
REV. B
ADG528A/ADG529A
–5–
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
1
ADG528AKN –40°C to +85°C PDIP N-18
ADG528AKP –40°C to +85°C PLCC P-20A
ADG528AKP-REEL –40°C to +85°C PLCC P-20A
ADG528ABQ –40°C to +85°C CERDIP Q-18
ADG528ATQ –55°C to +125°C CERDIP Q-18
ADG528ABCHIPS DIE
ADG528ATCHIPS DIE
ADG529AKN –40°C to +85°C PDIP N-18
ADG529AKP –40°C to +85°C PLCC P-20A
ADG529AKRW –40°C to +85°C SOIC RW-18
ADG529AKRW-REEL –40°C to +85°C SOIC RW-18
ADG529AKRW-REEL7 –40°C to +85°C SOIC RW-18
ADG529ABQ –40°C to +85°C CERDIP Q-18
ADG529ATQ –55°C to +125°C CERDIP Q-18
ADG529ABCHIPS DIE
ADG529ATCHIPS DIE
NOTES
1
N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip; RW = SOIC.
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= +25°C, unless otherwise noted)
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 V
Analog Inputs
2
Voltage at S, D . . . . . . . . . V
SS
– 2 V to V
DD
+ 2 V or 20 mA,
whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . 20 mA
Pulsed Current, S or D
1 ms duration, 10% Duty Cycle . . . . . . . . . . . . . . . 40 mA
Digital Inputs
1
Voltage at A, EN, WR, RS . . . . . . V
SS
– 4 V to V
DD
+ 4 V or
20 mA, whichever Occurs First
Power Dissipation (Any Package)
Up to +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 mW
Derates above +75°C . . . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature
Commercial (K Version) . . . . . . . . . . . . . . . –40°C to +85°C
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2
Overvoltage at A, EN, WR, RS, S or D will be clamped by diodes. Current should
be limited to the maximum rating above.
PIN CONFIGURATIONS
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADG528A/ADG529A features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PLCCDIP/SOIC
REV. B–6–
ADG528A/ADG529A
TRUTH TABLES
A2 A1 A0 EN WR RS ON SWITCH PAIR
XXXX
1Retains Previous Switch Condition
XXXX X 0 NONE (Address and Enable
Latches Cleared)
XXX0 0 1 NONE
0001 0 11
0011 0 12
0101 0 13
0111 0 14
1001 0 15
1011 0 16
1101 0 17
1111 0 18
X = Don’t Care ADG528A
A1 A0 EN WR RS ON SWITCH PAIR
XXX
1Retains Previous Switch Condition
XXX X0NONE (Address and Enable Latches
Cleared)
XX0 01NONE
001 0 1 1
011 0 1 2
101 0 1 3
111 0 1 4
X = Don’t Care ADG529A
TIMING DIAGRAMS
Figure 1.
Figure 2.
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive; there-
fore, while WR is held low, the latches are transparent and the
switches respond to the address and enable inputs. This input
data is latched on the rising edge of WR.
Figure 2 shows the Reset Pulse Width, t
RS
, and Reset Turn-off
Time, t
OFF
(RS).
Note: All digital input signals rise and fall times measured from
10% to 90% of 3 V. t
R
= t
F
= 20 ns.

ADG528AKP-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Multiplexer Switch ICs 8:1 280 Ohm Latchable
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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