AD8350ARMZ20-REEL7

REV.
AD8350
–9–
For the output matching network, if the output source resis-
tance of the AD8350 is greater than the terminating load
resistance, a step-down network should be employed as shown
on the output of Figure 3. For a step-down matching network,
the series and parallel reactances are calculated as:
X
RR
X
XR
R
RR
S
S LOAD
P
PS
LOAD
S LOAD
=
×
where
(2)
For a 10 MHz application with the 200 Ω output source resistance
of the AD8350, R
S
= 200 Ω, and a 50 Ω load termination, R
LOAD
=
50 Ω, then X
P
= 115.5 Ω and X
S
= 86.6 Ω, which results in
the following component values:
C
P
= (2 π × 10 × 10
6
× 115.5)
–1
= 138 pF and
L
S
= 86.6 × (2 π × 10 × 10
6
)
–1
= 1.38 μH
The same results can be obtained using the plots in Figure 5
and Figure 6. Figure 5 shows the normalized shunt reactance
versus the normalized source resistance for a step-up matching
network, R
S
< R
LOAD
. By inspection, the appropriate reactance
can be found for a given value of R
S
/R
LOAD
. The series reactance
is then calculated using X
S
= R
S
R
LOAD
/X
P.
The same technique
can be used to design the step-down matching network using
Figure 6.
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0.01
0.05
0.09
0.13
0.17
0.21
0.25
0.29
0.33
0.37
0.41
0.45
0.49
0.53
0.57
0.61
0.65
0.69
0.73
0.77
NORMALIZED REACTANCE – X
P
/R
LOAD
NORMALIZED SOURCE RESISTANCE – R
SOURCE
/R
LOAD
R
SOURCE
X
S
R
LOAD
X
P
Figure 5. Normalized Step-Up Matching Components
NORMALIZED REACTANCE – X
P
/R
LOAD
NORMALIZED SOURCE RESISTANCE – R
SOURCE
/R
LOAD
3.2
3
2.8
2.6
2.4
2.2
2
2
2.4
2.8
3.2
3.6
4
4.4
4.8
5.2
5.6
6
6.4
6.8
7.2
7.6
8
8.4
8.8
R
SOURCE
X
S
R
LOAD
X
P
Figure 6. Normalized Step-Down Matching Components
The same results could be found using a Smith Chart as shown
in Figure 7. In this example, a shunt capacitor and a series inductor
are used to match the 200 Ω source to a 50 Ω load. For a fre-
quency of 10 MHz, the same capacitor and inductor values
previously found using the resonant approach will transform the
200 Ω source to match the 50 Ω load. At frequencies exceeding
100 MHz, the S parameters from Tables II and III should be
used to account for the complex impedance relationships.
SOURCE
LOAD
SHUNT C
SERIES L
Figure 7. Smith Chart Representation of Step-Down Network
After determining the matching network for the single-ended
equivalent circuit, the matching elements need to be applied in a
differential manner. The series reactance needs to be split such
that the final network is balanced. In the previous examples, this
simply translates to splitting the series inductor into two equal
halves as shown in Figure 3.
Gain Adjustment
The effective gain of the AD8350 can be reduced using a num-
ber of techniques. Obviously a matched attenuator network will
reduce the effective gain, but this requires the addition of a
separate component which can be prohibitive in size and cost.
The attenuator will also increase the effective noise figure resulting
in an SNR degradation. A simple voltage divider can be imple-
mented using the combination of the driving impedance of the
previous stage and a shunt resistor across the inputs of the AD8350
as shown in Figure 8. This provides a compact solution but
suffers from an increased noise spectral density at the input
of the AD8350 due to the thermal noise contribution of the
shunt resistor. The input impedance can be dynamically altered
through the use of feedback resistors as shown in Figure 9. This
will result in a similar attenuation of the input signal by virtue
of the voltage divider established from the driving source imped-
ance and the reduced input impedance of the AD8350. Yet
this technique does not significantly degrade the SNR with
the unnecessary increase in thermal noise that arises from a truly
resistive attenuator network.
C
REV.
AD8350
–10–
V
S
876
5
1234
AD8350
+
ENBL (5V)
+V
S
(5V TO 10V)
0.1F
C
AC
R
S
C
AC
C
AC
C
AC
R
SHUNT
R
SHUNT
R
S
R
L
R
L
Figure 8. Gain Reduction Using Shunt Resistor
V
S
876
5
1234
AD8350
+
ENBL
(5V)
+V
S
(5V TO 10V)
0.1F
R
S
C
AC
C
AC
R
S
R
L
R
L
C
AC
C
AC
R
FEXT
R
FEXT
Figure 9. Dynamic Gain Reduction
Figure 8 shows a typical implementation of the shunt divider
concept. The reduced input impedance that results from the
parallel combination of the shunt resistor and the input impedance
of the AD8350 adds attenuation to the input signal effectively
reducing the gain. For frequencies less than 100 MHz, the input
impedance of the AD8350 can be modeled as a real 200 Ω resis-
tance (differential). Assuming the frequency is low enough to
ignore the shunt reactance of the input, and high enough such
that the reactance of moderately sized ac-coupling capacitors
can be considered negligible, the insertion loss, IL, due to the
shunt divider can be expressed as:
IL dB Log
R
RR
RR
RR R
RR
RR
RR
R gl nded
IN
IN S
IN SHUNT
IN SHUNT S
IN SHUNT
IN SHUNT
IN SHUNT
IN
()
()
()
+
+
=
×
+
=−
20
100
10
where
and Ω sin e e
(3)
The insertion loss and the resultant power gain for multiple
shunt resistor values is summarized in Table I. The source
resistance and input impedance need careful attention when
using Equation 1. The reactance of the input impedance of the
AD8350 and the ac-coupling capacitors need to be considered
before assuming they have negligible contribution. Figure 10
shows the effective power gain for multiple values of R
SHUNT
for
the AD8350-15 and AD8350-20.
Table I. Gain Adjustment Using Shunt Resistor,
R
S
= 100 and R
IN
= 100 Single-Ended
Power Gain–dB
R
SHUNT
IL–dB AD8350-15 AD8350-20
50 6.02 8.98 13.98
100 3.52 11.48 16.48
200 1.94 13.06 18.06
300 1.34 13.66 18.66
400 1.02 13.98 18.98
R
SHUNT
20
0
GAIN – dB
18
16
14
12
10
8
6
4
2
0
100 200 300 400 500 600 700 800
AD8350-20
AD8350-15
Figure 10. Gain for Multiple Values of Shunt Resistance
for Circuit in Figure 8
The gain can be adjusted dynamically by employing external
feedback resistors as shown in Figure 9. The effective attenua-
tion is a result of the lowered input impedance as with the shunt
resistor method, yet there is no additional noise contribution at
the input of the device. It is necessary to use well-matched resistors
to minimize common-mode offset errors. Quality 1% tolerance
resistors should be used along with a symmetric board layout to
help guarantee balanced performance. The effective gain for mul-
tiple values of external feedback resistors is shown in Figure 11.
C
REV.
AD8350
–11–
R
FEXT
20
0
GAIN – dB
18
16
14
12
10
8
6
4
2
0
500 1000 1500 2000
AD8350-20
AD8350-15
Figure 11. Power Gain vs. External Feedback Resistors
for the AD8350-15 and AD8350-20 with R
S
= 100
Ω
and
R
L
= 100
Ω
The power gain of any two-port network is dependent on the
source and load impedance. The effective gain will change if the
differential source and load impedance is not 200 Ω. The single-
ended input and output resistance of the AD8350 can be modeled
using the following equations:
R
RR
RR
R
gR
IN
FL
FL
INT
mL
=
+
+
++ ×1
(4)
and
R
R
RR
g
RR
RR
gR
for R k
OUT
F
S INT
m
S INT
FS
mS
S
=
+
+
+
+
1
11
1
1
11
1
1 Ω
(5)
where
R
F
=R
FEXT
//R
FINT
R
FEXT
= R Feedback External
R
FINT
= 662 Ω for the AD8350-15
= 1100 Ω for the AD8350-20
R
INT
= 25000 Ω
g
m
= 0.066 mhos for the AD8350-15
= 0.110 mhos for the AD8350-20
R
S
= R Source (Single-Ended)
R
L
= R Load (Single-Ended)
R
IN
= R Input (Single-Ended)
R
OUT
= R Output (Single-Ended)
The resultant single-ended gain can be calculated using the
following equation:
G
RgR
RRRRRg
V
LmF
LSF LSm
=
××
()
+++××
1
(6)
Driving Lighter Loads
It is not necessary to load the output of the AD8350 with a
200 Ω differential load. Often it is desirable to try to achieve a
complex conjugate match between the source and load in order
to minimize reflections and conserve power. But if the AD8350
is driving a voltage responding device, such as an ADC, it is no
longer necessary to maximize power transfer. The harmonic
distortion performance will actually improve when driving
loads greater than 200 Ω. The lighter load requires less cur-
rent driving capability on the output stages of the AD8350
resulting in improved linearity. Figure 12 shows the improve-
ment in second and third harmonic distortion for increasing
differential load resistance.
R
LOAD
–66
200
DISTORTION – dBc
–68
–70
–72
–74
–76
–78
–80
–82
300 400 500 600 700 800 900 1000
HD3
HD2
Figure 12. Second and Third Harmonic Distortion vs.
Differential Load Resistance for the AD8350-15 with
V
S
= 5 V, f = 70 MHz, and V
OUT
= 1 V p-p
C

AD8350ARMZ20-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
RF Amplifier IC RF/IF 1 GHz
Lifecycle:
New from this manufacturer.
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