Philips Semiconductors Product data
P80C3xX2; P80C5xX2;
P87C5xX2
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
2003 Jan 24
43
AC ELECTRICAL CHARACTERISTICS (6-CLOCK MODE, 2.7 V TO 5.5 V OPERATION)
T
amb
= 0 °C to +70 °C or –40 °C to +85 °C ; V
CC
=2.7 V to 5.5 V, V
SS
= 0 V
1,2,3,4,5
Symbol Figure Parameter
Limits 16 MHz Clock
Unit
MIN MAX MIN MAX
1/t
CLCL
31 Oscillator frequency 0 16 – – MHz
t
LHLL
27 ALE pulse width t
CLCL
–10 – 52.5 – ns
t
AVLL
27 Address valid to ALE low 0.5 t
CLCL
–15 – 16.25 – ns
t
LLAX
27 Address hold after ALE low 0.5 t
CLCL
–25 – 6.25 – ns
t
LLIV
27 ALE low to valid instruction in – 2 t
CLCL
–55 – 70 ns
t
LLPL
27 ALE low to PSEN low 0.5 t
CLCL
–15 – 16.25 – ns
t
PLPH
27 PSEN pulse width 1.5 t
CLCL
–15 – 78.75 – ns
t
PLIV
27 PSEN low to valid instruction in – 1.5 t
CLCL
–55 – 38.75 ns
t
PXIX
27 Input instruction hold after PSEN 0 – 0 – ns
t
PXIZ
27 Input instruction float after PSEN – 0.5 t
CLCL
–10 – 21.25 ns
t
AVIV
27 Address to valid instruction in – 2.5 t
CLCL
–50 – 101.25 ns
t
PLAZ
27 PSEN low to address float – 10 – 10 ns
Data Memory
t
RLRH
28 RD pulse width 3 t
CLCL
–25 – 162.5 – ns
t
WLWH
29 WR pulse width 3 t
CLCL
–25 – 162.5 – ns
t
RLDV
28 RD low to valid data in – 2.5 t
CLCL
–50 – 106.25 ns
t
RHDX
28 Data hold after RD 0 – 0 – ns
t
RHDZ
28 Data float after RD – t
CLCL
–20 – 42.5 ns
t
LLDV
28 ALE low to valid data in – 4 t
CLCL
–55 – 195 ns
t
AVDV
28 Address to valid data in – 4.5 t
CLCL
–50 – 231.25 ns
t
LLWL
28, 29 ALE low to RD or WR low 1.5 t
CLCL
–20 1.5 t
CLCL
+20 73.75 113.75 ns
t
AVWL
28, 29 Address valid to WR low or RD low 2 t
CLCL
–20 – 105 – ns
t
QVWX
29 Data valid to WR transition 0.5 t
CLCL
–30 – 1.25 – ns
t
WHQX
29 Data hold after WR 0.5 t
CLCL
–20 – 11.25 – ns
t
QVWH
29 Data valid to WR high 3.5 t
CLCL
–10 – 208.75 – ns
t
RLAZ
28 RD low to address float – 0 – 0 ns
t
WHLH
28, 29 RD or WR high to ALE high 0.5 t
CLCL
–15 0.5 t
CLCL
+15 16.25 46.25 ns
External Clock
t
CHCX
31 High time 0.4 t
CLCL
t
CLCL
– t
CLCX
– – ns
t
CLCX
31 Low time 0.4 t
CLCL
t
CLCL
– t
CHCX
– – ns
t
CLCH
31 Rise time – 5 – – ns
t
CHCL
31 Fall time – 5 – – ns
Shift register
t
XLXL
30 Serial port clock cycle time 6 t
CLCL
– 375 – ns
t
QVXH
30 Output data setup to clock rising edge 5 t
CLCL
–25 – 287.5 – ns
t
XHQX
30 Output data hold after clock rising edge t
CLCL
–15 – 47.5 – ns
t
XHDX
30 Input data hold after clock rising edge 0 – 0 – ns
t
XHDV
30 Clock rising edge to input data valid – 5 t
CLCL
–133 – 179.5 ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN
=100 pF, load capacitance for all outputs = 80 pF
3. Interfacing the microcontroller to devices with float time up to 45ns is permitted. This limited bus contention will not cause damage to port 0
drivers.
4. Parts are guaranteed by design to operate down to 0 Hz.
5. Data shown in the table are the best mathematical models for the set of measured values obtained in tests. If a particular parameter
calculated at a customer specified frequency has a negative value, it should be considered equal to zero.
