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NCD1015-LGA

P1-P3P4-P6P7-P9P10-P12P13-P13
I
NTEGRATED
C
IRCUITS
D
IVISION
NCD1015-LGA
10 PRELIMINARY R00A
5.2 CRC-CCITT ERROR CHECKING
The CRC error checking circuitry generates a 16-bit CRC to ensure the integrity of transmitted and received data
packets. The reader and transponder use the CRC-CCITT (Consultative Committee for International Telegraph and
Telephone) for error detection.
The 16-bit Write Frame BCC is generated by the transponder on reception of the complete write data stream to
validate the correct data transmission.
Figure 10: Schematic Diagram of the 16-Bit CRC-CCITT Generator
The 16 bits cyclic redundancy code is calculated using the following polynomial with an initial value of 0000hex:
P(X) = x
16
+ x
12
+ x
5
+ x
0
The implemented version of the CRC check has the following characteristics:
• Reverse CRC-CCITT 16 as described in ISO/IEC 13239 and used in ISO/IEC 11784/11785
• The CRC 16-bit shift register is initialized to all zeros at the beginning of a request
• The incoming data bits are XOR-ed with the MSB of the CRC register, and are shifted into the register's LSB
• After all data bits have been processed, the CRC register contains the CRC-16 code
• Reversibility - The original data together with associated CRC, when fed back into the same CRC generator will
regenerate the initial value (all zero's)
6. Memory
6.1 Memory Block
The memory is structured into 8 Blocks of 32 bits each. In addition a Lock Bit is provided as Bit 0 corresponding to
each Block. Two Blocks form one Page, of which 2 exist. The following table shows the memory organization.
6.1.1 Page 1 - Identification Data
Page 1 is used for the Identification Data as specified in ISO/ IEC 11784. This page is locked if the Lock Bits of the
corresponding Blocks are set to "1". If the Page is locked, the stored value can not be overwritten.
6.1.2 Page 4 - Configuration Register + Management Register
Page 4 consists of Block 0, which is the Management Register, as the Most Significant Bits and the Block 7, which is
the Configuration Register as the Least Significant Bits of it. This Page is locked if the Lock Bits of the corresponding
Blocks are set to "1". If the Page is locked, the stored value can not be overwritten.
Block Address Page Address Description
0 4 Management Register / MSB
1
1
Identification Data / LSB
2 Identification Data / MSB
7 4 Configuration Register / LSB
P (X) = X0X1X2X3X4 X5X6X7X8X9X10X11 X12X13X14X15
MSB
Data in
LSB
I
NTEGRATED
C
IRCUITS
D
IVISION
NCD1015-LGA
R00A PRELIMINARY 11
Configuration Register
The configuration register (CREG) layout is depicted in Figure 11.
If the flag DISCH is '1' and the system is in 'Normal Mode', the storage capacitance is not going to be discharged.
The trimming bits specify the trimming vector for the capacitor in the analog part.
Figure 11: Configuration Register (CREG) Layout
LOCK: Lock bit
DISCH: Discharge (0=discharge, 1=no discharge)
Management Register
The management register (MREG) contains information about the current state of the system.
Figure 12: Management Register (MREG) Layout
LOCK: Lock bit
XX: Undefined
MGM Key: Management key [3:0]
The contents of the Management key are explained in the following table.
Normal mode
In Normal mode all the commands explained before are valid.
All blocks locked
Blocking MREG while the "Management key" has the 0110 value ("All Blocks Locked") leads to the "All Blocks
Locked” state. In this state the memory is protected against writing; this state is irreversible.
DISCHG LOCK
32 30 0
xx MGM Key LOCK
32 410
Key Value Description
MSB LSB
0000 Normal Mode - by Default
0110 All Blocks Locked
I
NTEGRATED
C
IRCUITS
D
IVISION
NCD1015-LGA
12 PRELIMINARY R00A
7 Manufacturing Information
7.1 Moisture Sensitivity
All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated
Circuits Division classified all of its plastic encapsulated devices for moisture sensitivity according to the
latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product
evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee
proper operation of our devices when handled according to the limitations and information in that standard as well as
to any limitations set forth in the information or standards referenced below.
Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced
product performance, reduction of operable life, and/or reduction of overall reliability.
This product carries a Moisture Sensitivity Level (MSL) rating as shown below, and should be handled according to
the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033.
7.2 ESD Sensitivity
This product is ESD Sensitive, and should be handled according to the industry standard
JESD-625.
7.3 Reflow Profile
This product has a maximum body temperature and time rating as shown below. All other guidelines of
J-STD-020 must be observed.
7.4 Board Wash
IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. However, board washing to
remove flux residue is acceptable, and the use of a short drying bake may be necessary. Chlorine-based or
Fluorine-based solvents or fluxes should not be used. Cleaning methods that employ ultrasonic energy should not be
used.
Device Moisture Sensitivity Level (MSL) Rating
NCD1015-LGA MSL TBD
Device Maximum Temperature x Time
NCD1015-LGA TBD
P1-P3P4-P6P7-P9P10-P12P13-P13

NCD1015-LGA

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Manufacturer:
IXYS Integrated Circuits
Description:
RFID Transponders HDX RFID IC
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