Si552
10 Rev. 1.2
3. Ordering Information
The Si552 supports a variety of options including frequency, temperature stability, tuning slope, output format, and
V
DD
. Specific device configurations are programmed into the Si552 at time of shipment. Configurations are
specified using the Part Number Configuration chart shown below. Silicon Labs provides a web browser-based part
number configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to access this tool
and for further ordering instructions. The Si552 VCXO series is supplied in an industry-standard, RoHS-compliant,
lead-free, 6-pad, 5 x 7 mm package. Tape and reel packaging is an ordering option.
Figure 1. Part Number Convention
DD
R = Tape & Reel
Blank = Coil Tape
Operating Temp Range (°C)
G –40 to +85 °C
Device Revision Letter
552 Dual VCXO
Product Family
1
st
Option Code
Code VDD Output Format
A 3.3 LVPECL
B3.3LVDS
C3.3CMOS
D3.3CML
E 2.5 LVPECL
F2.5LVDS
G2.5CMOS
H2.5CML
J1.8CMOS
K1.8CML
Notes:
CMOS available to 160 MHz.
552
X X
XXXXXX
D G R
2
nd
Option Code
Temperature Tuning Slope Minimum APR
Stability Kv (±ppm) for VDD @
Code ± ppm (max) ppm/V (typ) 3.3 V 2.5 V 1.8 V
A 100 180 100 75 25
B 100 90 30 Note 6 Note 6
C 50 180 150 125 75
D5090803025
E 20 45 25 Note 6 Note 6
F 50 135 100 75 50
G 20 356 375 300 235
H 20 180 185 145 105
J 20 135 130 104 70
K 100 356 295 220 155
M 20 33 12 Note 6 Note 6
Notes:
1. For best jitter and phase noise performance , always choose the smallest Kv that meets
the application s minimum APR requirements. Unlike SAW-based solutions which
require higher higher Kv values to account for their higher temperature dependence ,
the Si55x series provides lower Kv options to minimize noise coupling and jitter in real -
world PLL designs. See AN255 and AN266 for more information.
2. APR is the ability of a VCXO to track a signal over the product lifetime . A VCXO with an
APR of ±25 ppm is able to lock to a clock with a ± 25 ppm stability over 15 years over all
operating conditions.
3. Nominal Pull range (±) = 0.5 x V
DD
x tuning slope.
4. Nominal Absolute Pull Range (±APR) = Pull range – stability – lifetime aging
= 0.5 x V
DD
x tuning slope – stability – 10 ppm
5. Minimum APR values noted above include worst case values for all parameters .
6. Combination not available.
Example Part Number: 552AF000108DGR is a 5x7mm Dual VCXO in a 6 pad package. Since the six digit code (000108) is >
000100, f0 is 644.53125 MHz (lower frequency) and f1 is 693.48299 (higher frequency), with a 3.3V supply and LVPECL output.
Temperature stability is specified as ± 50 ppm and the tuning slope is 135 ppm/V. The part is specified for a -40 to +85 C° ambient
temperature range operation and is shipped in tape and reel format .
6-digit Frequency Designator Code
Two unique frequencies can be specified within the following bands of frequencies : 10 to
945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz. A six digit code will be assigned for
the specified combination of frequencies . Codes > 000100 refer to dual XOs programmed
with the lower frequency value selected when FS = 0, and the higher value when FS = 1.
Six digit codes < 000100 refer to dual XOs programmed with the higher frequency value
selected when FS = 0, and the lower value when FS = 1.
Si552
Rev. 1.2 11
4. Package Outline and Suggested Pad Layout
Figure 2 illustrates the package details for the Si552. Table 12 lists the values for the dimensions shown in the
illustration.
Figure 2. Si552 Outline Diagram
Table 12. Package Diagram Dimensions (mm)
Dimension Min Nom Max
A 1.50 1.65 1.80
b 1.30 1.40 1.50
c 0.50 0.60 0.70
D 5.00 BSC
D1 4.30 4.40 4.50
e 2.54 BSC.
E 7.00 BSC.
E1 6.10 6.20 6.30
H 0.55 0.65 0.75
L 1.17 1.27 1.37
p 1.80 2.60
R 0.70 REF
aaa 0.15
bbb 0.15
ccc 0.10
ddd 0.10
eee 0.50
Si552
12 Rev. 1.2
5. 6-Pin PCB Land Pattern
Figure 3 illustrates the 6-pin PCB land pattern for the Si552. Table 13 lists the values for the dimensions shown in
the illustration.
Figure 3. Si552 PCB Land Pattern
Table 13. PCB Land Pattern Dimensions (mm)
Dimension Min Max
D2 5.08 REF
e 2.54 BSC
E2 4.15 REF
GD 0.84
GE 2.00
VD 8.20 REF
VE 7.30 REF
X1.70 TYP
Y2.15 REF
ZD 6.78
ZE 6.30
Notes:
1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification.
2. Land pattern design based on IPC-7351 guidelines.
3. All dimensions shown are at maximum material condition (MMC).
4. Controlling dimension is in millimeters (mm).

552AC000471DG

Mfr. #:
Manufacturer:
Silicon Labs
Description:
VCXO Oscillators Differential/single-ended dual frequency VCXO; 10-1417 MHz
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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