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XRD98L61EVAL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38
XRD98L61
10
Rev. 2.00
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Offset OB[7] OB[6] OB[5] OB[4] OB[3] OB[2] OB[1] OB[0]
Default 0 0 1 0 0 0 0 0 0 0
Offset Register (Reg. 1, Address 000001)
The Offset register is used to set the target ADC output code for Optical Black pixels.
See the Black Level Offset Calibration section for more information.
Table 1. Serial Interface Register Address Map & default values
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Gain
PGA[9] PGA[8] PGA[7] PGA[6] PGA[5] PGA[4] PGA[3] PGA[2] PGA[1]
PGA[0]
Default
0 0 0 0 0 0 0 0 0 0
The Gain register is used to set the gain of the Programmable Gain Amplifier (PGA).
Code 0000000000 is minimum gain (0 dB). Codes 1011111111 and greater are maximum gain (36 dB).
See the Programmable Gain Amplifier (PGA) section for more information.
Gain Register (Reg. 0, Address 000000)
Address bits
Data bits
Reg. Name A5 A4 A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Gain 0 0 0 0 0 0
PGA[9]
0
PGA[8]
0
PGA[7]
0
PGA[6]
0
PGA[5]
0
PGA[4]
0
PGA[3]
0
PGA[2]
0
PGA[1]
0
PGA[0]
0
Offset 0 0 0 0 0 1
OB[7]
1
OB[6]
0
OB[5]
0
OB[4]
0
OB[3]
0
OB[2]
0
OB[1]
0
OB[0]
0
Calibration 0 0 0 0 1 0
Avg[2]
1
Avg[1]
0
Avg[0]
1
Mode
0
LFrame
0
DNS[1]
1
DNS[0]
1
FastCal
1
Hold
0
ManCal
0
Wait A 0 0 0 0 1 1
WL[11]
0
WL[10]
0
WL[9]
0
WL[8]
0
WL[7]
0
WL[6]
0
WL[5]
0
WL[4]
0
WL[3]
0
WL[2]
0
Wait B 0 0 0 1 0 0
WL[1]
0
WL[0]
1
OB Lines 0 0 0 1 0 1
OBL[7]
0
OBL[6]
0
OBL[5]
0
OBL[4]
0
OBL[3]
0
OBL[2]
0
OBL[1]
1
OBL[0]
0
CDAC 0 0 0 1 1 0
CDAC[8]
0
CDAC[7]
0
CDAC[6]
0
CDAC[5]
0
CDAC[4]
0
CDAC[3]
0
CDAC[2]
0
CDAC[1]
0
CDAC[0]
0
FDAC 0 0 0 1 1 1
FDAC[9]
0
FDAC[8]
0
FDAC[7]
0
FDAC[6]
0
FDAC[5]
0
FDAC[4]
0
FDAC[3]
0
FDAC[2]
0
FDAC[1]
0
FDAC[0]
0
Control 0 0 1 0 0 0
DIGtest
0
ADCtest
0
NoCDS
0
LowPwr
0
OE
1
DAC1pd
1
DAC0pd
1
AFEpd
0
ADCpd
0
PwrDwn
0
Polarity 0 0 1 0 0 1
SBLKpol
0
SPIXpol
0
CALpol
0
CLAMPpol
0
*Reserved
0
ADCpol
0
Clock 0 0 1 0 1 0
CLKtest
0
Nullamp
0
CMtest
0
Fastclk
0
CLAMPopt
0
OneShot
0
ClampCal
0
SPIXopt
0
RSTreject
0
VSreject
0
Delay A 0 0 1 0 1 1
DelayA[8]
0
DelayA[7]
0
DelayA[6]
0
DelayA[5]
0
DelayA[4]
0
DelayA[3]
0
DelayA[2]
0
DelayA[1]
0
DelayA[0]
0
Delay B 0 0 1 1 0 0
DelayB[8]
0
DelayB[7]
0
DelayB[6]
0
DelayB[5]
0
DelayB[4]
0
DelayB[3]
0
DelayB[2]
0
DelayB[1]
0
DelayB[0]
0
DAC0 0 0 1 1 0 1
DAC0[7]
0
DAC0[6]
0
DAC0[5]
0
DAC0[4]
0
DAC0[3]
0
DAC0[2]
0
DAC0[1]
0
DAC0[0]
0
DAC1 0 0 1 1 1 0
DAC1[7]
0
DAC1[6]
0
DAC1[5]
0
DAC1[4]
0
DAC1[3]
0
DAC1[2]
0
DAC1[1]
0
DAC1[0]
0
ReadBack 1 1 1 1 1 0
RBenable
0
RBreg[8]
0
RBreg[7]
0
RBreg[6]
0
RBreg[5]
0
RBreg[4]
0
RBreg[3]
0
RBreg[2]
0
RBreg[1]
0
RBreg[0]
0
Reset 1 1 1 1 1 1
Reset
0
NOTE: *Reserved Test register bit. Used for factory test only. Please do not modify.
11
Rev. 2.00
XRD98L61
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
OB Lines OBL[7] OBL[6] OBL[5] OBL[4] OBL[3] OBL[2] OBL[1] OBL[0]
Default 0 0 0 0 0 0 0 0 1 0
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Calibration Avg[2] Avg[1] Avg[0] Mode
LFrame
DNS[1] DNS[0]
FastCal
Hold
ManCal
Default 1 0 1 0 0 1 1 1 0 0
The Calibration register is used to set various options for the Black Level Offset Calibration.
Avg[2:0] set the number of OB pixels to average:
000 = 4 pixels (not recommended) 100 = 64 pixels
001 = 8 pixels (not recommended) 101 = 128 pixels (default)
010 = 16 pixels (not recommended) 110 = 256 pixels
011 = 32 pixels 111 = 512 pixels
Mode=0, selects Line mode calibration (use OB pixels at start or end of each line).
Mode=1, do not use.
LFrame=0, selects Line mode calibration.
LFrame=1, do not use.
DNS[1:0] selects the Digital Noise Suppression filter setting:
00 = off, 10 = medium,
01 = narrow, 11 = wide.
FastCal=0, disables speedup convergence option of the calibration feedback loop.
FastCal=1, enables an option to speedup convergence of the calibration feedback loop.
Hold=0, normal operation of calibration feedback loop.
Hold=1, stops all updates to the Coarse and Fine offset DAC accumulators.
ManCal=0, normal operation of calibration feedback loop.
ManCal=1, enables manual calibration. The offset DACs are set to the values in the CDAC and FDAC registers.
See the Black Level Offset Calibration section for more information.
WaitA Register (Reg. 3, Address 000011)
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
WaitB WL[1] WL[0]
Default 0 0 0 0 0 0 0 0 0 1
WaitB Register (Reg. 4, Address 000100)
The WaitA and WaitB registers are concatenated to make up the Wait register.
See OB Pixel calibration section for more information.
OB Lines Register (Reg. 5, Address 000101)
The OB Lines register is used by the Offset Calibration Logic to set the number of Optical Black lines used
for Calibration in the Frame Mode. Do not use.
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
WaitA WL[11] WL[10] WL[9] WL[8] WL[7] WL[6] WL[5] WL[4] WL[3] WL[2]
Default 0 0 0 0 0 0 0 0 0 0
Calibration Register (Reg. 2, Address 000010)
XRD98L61
12
Rev. 2.00
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Control DIGtest ADCtest NoCDS LowPwr OE DAC1pd DAC0pd AFEpd ADCpd PwrDwn
Default 0 0 0 0 1 1 1 0 0 0
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
FDAC FDAC[9] FDAC[8] FDAC[7] FDAC[6] FDAC[5] FDAC[4] FDAC[3] FDAC[2] FDAC[1] FDAC[0]
Default 0 0 0 0 0 0 0 0 0 0
FDAC Register (Reg. 7, Address 000111)
The FDAC register is used to set the Fine Offset DAC in the Manual Calibration mode. See Calibration
Option, in the Black Level Offset Calibration section for more information.
Control Register (Reg. 8, Address 001000)
The Control register is used to set various test and power-down modes.
DIGtest=0, normal operation.
DIGtest=1, Exar test mode - do not use.
ADCtest=0, connects PGA output to ADC input.
ADCtest=1, connects ADCinP & ADCinN pins to ADC input.
NoCDS=0, connects CDS output to PGA input.
NoCDS=1, connects Test1 & Test2 pins to PGA inputs (CDS by-pass mode).
Low Power=0, normal operation.
Low Power=1, Exar test mode - do not use.
OE=0, digital outputs in high-Z state.
OE=1, digital outputs enabled.
DAC1pd=1, Utility DAC1 is powered down.
DAC0pd=1, Utility DAC0 is powered down.
AFEpd=0, normal operation.
AFEpd=1, CDS & PGA are powered down, do not use.
ADCpd=0, normal operation.
ADCpd=1, ADC is powered down, do not use.
PwrDwn=0, normal operation.
PwrDwn=1, the whole chip is powered down.
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CDAC CDAC[8] CDAC[7] CDAC[6] CDAC[5] CDAC[4] CDAC[3] CDAC[2] CDAC[1] CDAC[0]
Default 0 0 0 0 0 0 0 0 0 0
CDAC Register (Reg. 6, Address 000110)
The CDAC register is used to set the Coarse Offset DAC in the Manual Calibration mode.
See Calibration Option, in the Black Level Offset Calibration section for more information.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38

XRD98L61EVAL

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Manufacturer:
MaxLinear
Description:
Data Conversion IC Development Tools Eval Board for XRD98L61AIV
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