6.42
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
12
Timing Waveform with Port-to-Port Flow-Through Read
(1,2,3,5)
DATA
IN "A"
CLK
"B"
R/W
"B"
ADDRESS
"A"
R/W
"A"
CLK
"A"
ADDRESS
"B"
NO
MATCH
MATCH
NO
MATCH
MATCH
VALID
t
CWDD
t
CD1
t
DC
DATA
OUT "B"
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VALID
VALID
t
SW
t
HW
t
SA
t
HA
t
SD
t
HD
t
HW
t
CD1
t
CCS
t
DC
t
SA
t
SW
t
HA
(4)
(4)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. CE
0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
3. OE = V
IL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
4. If t
CCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If t
CCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
5. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
Timing Waveform of Left Port Write to Pipelined Right Port Read
(1,2,4)
NOTES:
1. CE
0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = V
IL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to.
3. If t
CO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
t
CO + 2 tCYC2 + tCD2). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port
will be t
CO + tCYC2 + tCD2).
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
CLK
"A"
R/W
"A
"
ADDRESS
"A"
DATA
IN"A"
CLK
"B"
R/W
"B"
ADDRESS
"B"
DATA
OUT"B"
t
SW
t
HW
t
SA
t
HA
t
SD
t
HD
t
SW
t
HW
t
SA
t
HA
t
CO
(3)
t
CD2
NO
MATCH
VALID
NO
MATCH
MATCH
MATCH
VALID
3743 drw 10
t
DC