OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

NB7L111MMNR2

P1-P3P4-P6P7-P9P10-P12P13-P13
NB7L111M
www.onsemi.com
7
0
50
100
150
200
250
300
350
400
1 2 3 3.5 4 4.5 5 5.5 6 6.5
OUTPUT VOLTAGE AMPLITUDE (mV)
INPUT CLOCK FREQUENCY (GHz)
25
85
−40
Figure 3. Output Voltage Amplitude vs. Input
Clock Frequency and Temperature
(V
inpp
= 400 mV; V
CC
= 3.3 V)
0
50
100
150
200
250
300
350
400
1 2 3 3.5 4 4.5 5 5.5 6 6
.5
OUTPUT VOLTAGE AMPLITUDE (mV
)
INPUT CLOCK FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude vs. Input
Clock Frequency and Temperature
(V
inpp
= 75 mV; V
CC
= 3.3 V)
25
85
−40
0
50
100
150
200
250
300
350
400
1 2 3 3.5 4 4.5 5 5.5 6 6.5
0
50
100
150
200
250
300
350
400
1 2 3 3.5 4 4.5 5 5.5 6 6.5
INPUT CLOCK FREQUENCY (GHz)
OUTPUT VOLTAGE AMPLITUDE (mV)
−40
85
25
OUTPUT VOLTAGE AMPLITUDE (mV)
INPUT CLOCK FREQUENCY (GHz)
25
85
−40
Figure 5. Output Voltage Amplitude vs. Input
Clock Frequency and Temperature
(V
inpp
= 400 mV; V
CC
= 2.5 V)
Figure 6. Output Voltage Amplitude vs. Input
Clock Frequency and Temperature
(V
inpp
= 75 mV; V
CC
= 2.5 V)
Figure 7. Propagation Delay versus Temperature
−40 25 85
200
210
220
230
240
250
260
270
280
Temperature (°C)
PROPAGATION DELAY (ps)
Typical Tpd
NB7L111M
www.onsemi.com
8
Figure 8. Typical Output Waveform at 3.125 Gb/s with PRBS 2
23
−1 (V
inpp
= 75 mV−left and 400 mV−right)
Device DDJ = 6 ps
Device DDJ = 7 ps
VOLTAGE (50 mV/div)
TIME (22.1 ps/div)
VOLTAGE (50 mV/div)
TIME (22.1 ps/div)
Figure 9. Typical Output Waveform at 5 Gb/s with PRBS 2
23
−1 (V
inpp
=75 mV−left and 400 mV−right)
Device DDJ=16ps
Device DDJ=17ps
VOLTAGE (40 mv/ div)
TIME (22.1 ps/div)
VOLTAGE (40 mv/ div)
TIME (22.1 ps/div)
Figure 10. Typical Output Waveform at 6.125 Gb/s with PRBS 2
23
−1 (V
inpp
= 75 mV−left and 400 mV−right)
Device DDJ=12ps
Device DDJ=15ps
VOLTAGE (35 mv/div)
TIME (22.1 ps/div)
VOLTAGE (35 mv/div)
TIME (22.1 ps/div)
NB7L111M
www.onsemi.com
9
Figure 11. AC Reference Measurement
CLK
CLK
Q
Q
t
PHL
t
PLH
V
INPP
= V
IH
(CLK) − V
IL
(CLK)
V
OUTPP
= V
OH
(Q) − V
OL
(Q)
W
Receiver
Device
Q CLK
50
W
50
Figure 12. Typical Termination for 16 mA Output Drive and Device Evaluation
Q CLK
V
CC
W
50
W
50
V
CC
NB7L111M
CLK
V
th
CLK
V
th
Figure 13. Differential Input Driven
Single−Ended
CLK
CLK
Figure 14. Differential Inputs Driven
Differentially
V
IHmax
V
ILmax
V
IH
V
th
V
IL
V
IHmin
V
ILmin
V
CC
V
thmax
V
thmin
GND
V
th
V
IHDmax
V
ILDmax
V
IHDmin
V
ILDmin
V
IHDtyp
V
ILDtyp
V
ID
= V
IHD
− V
ILD
V
CMR
V
CC
V
CMmax
V
CMmax
GND
Figure 15. V
th
Diagram Figure 16. V
CMR
Diagram
P1-P3P4-P6P7-P9P10-P12P13-P13

NB7L111MMNR2

Mfr. #:
Buy NB7L111MMNR2
Manufacturer:
ON Semiconductor
Description:
Clock Drivers & Distribution 2.5V/3.3V 6.125Gb/s
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet