2 of 2 October 18, 2007
IDT 89HPES24T3G2 Product Brief
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
for Tech Support:
email: ssdhelp@idt.com
phone: 408-284-8208
NOT AN OFFER FOR SALE
The information presented herein is subject to a Non-Disclosure Agreement and is for planning purposes only. Nothing contained in this presenta-
tion, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
®
– Hot-swap capable I/O
– External Serial EEPROM contents are checksum protected
– Supports PCI Express Device Serial Number Capability
– Capability to monitor link reliability and autonomously change
link speed to prevent link instability
◆
Power Management
– Utilizes advanced low-power design techniques to achieve low
typical power consumption
– Support PCI Power Management Interface specification (PCI-
PM 1.1)
• Supports device power management states: D0, D3
hot
and
D3
cold
– Support for PCI Express Active State Power Management
(ASPM) link state
• Supports link power management states: L0, L0s, L1, L2/L3
Ready and L3
– Supports PCI Express Power Budgeting Capability
– Configurable SerDes power consumption
• Supports optional PCI-Express SerDes Transmit Low-Swing
Voltage Mode
• Supports numerous SerDes Transmit Voltage Margin
settings
– Unused SerDes are disabled
◆
Testability and Debug Features
– Per port link up and activity status outputs available on I/O
expander outputs
– Built in SerDes 8-bit and 10-bit pseudo-random bit stream
(PRBS) generators
– Numerous SerDes test modes, including a PRBS Master
Loopback mode for in-system link testing
– Ability to read and write any internal register via SMBus and
JTAG interfaces, including SerDes internal controls
– Per port statistics and performance counters, as well as propri-
etary link status registers
◆
General Purpose Input/Output Pins
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
◆
Option A Package: 19mm x 19mm 324-ball Flip Chip BGA
with 1mm ball spacing
◆
Option B Package: 27mm x 27mm 676-ball Flip Chip BGA
with 1mm ball spacing
Product Description
Utilizing standard PCI Express interconnect, the PES24T3G2
provides the most efficient I/O connectivity solution for applications
requiring high throughput, low latency, and simple board layout with a
minimum number of board layers. It provides connectivity for up to 3
ports across 24 integrated serial lanes. Each lane provides 5 Gbps of
bandwidth in both directions and is fully compliant with PCI Express
Base Specification, Revision 2.0, including operation in 5 Gbps, 2.5
Gbps, and mixed 5 Gbps / 2.5Gbps modes.
The PES24T3G2 is based on a flexible and efficient layered architec-
ture. The PCI Express layer consists of SerDes, Physical, Data Link and
Transaction layers in compliance with PCI Express Base specification
Revision 2.0. The PES24T3G2 can operate either as a store and
forward or cut-through switch and is designed to switch memory and I/O
transactions. It supports eight Traffic Classes (TCs) and one Virtual
Channel (VC) with sophisticated resource management to enable effi-
cient switching and I/O connectivity for servers, storage, and embedded
processors with limited connectivity.
Figure 2 I/O Expansion Application
Memory
Memory
Memory
Processor
Memory
North
Bridge
PES24T3G2
I/O Dual
10GbE
I/O
SATA
I/O
SATA
PCI Express
Slot
Processor
x8
x8
x8
