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HW-XGI-SCLK-G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
10 www.xilinx.com Xilinx Generic Interface (XGI) SuperClock Module
UG091 (v1.1) March 2, 2007
Functional Description
R
The LVPECL frequency synthesizer receives a stable fundamental frequency from one of
two populated crystal oscillators (XTAL0, XTAL1) or by using the test clock input at SMA
J10. Reference clock input selection is set according to the input state of SEL0 and SEL1 as
defined in Table 2.
The feedback divider, using the states of M0, M1, and M2 as defined in Table 3, determines
the VCO output frequency. Floating inputs result in a default divisor of 32.
The reference clock output is divided by the states of inputs N0, N1, and N2 as defined in
Table 4. Floating inputs result in a default divisor of 4.
Table 2: Reference Clock Selection
Inputs
Reference PLL Mode
SEL0 SEL1
00XTAL0 Active
10XTAL1 Active
0 1 TEST_CLK Active
11TEST_CLKBypass
Table 3: M Divider Selection
Inputs
M Divider Value
Input Frequency
M0 M1 M2 Minimum Maximum
0 0 0 18 27.22 35.56
1 0 0 22 22.27 29.09
0 1 0 24 20.41 26.67
1 1 0 25 19.60 25.60
0 0 1 32 15.31 20.00
1 0 1 40 12.25 16.00
Table 4: N Divider Selection
Inputs
N Divider Value
N0 N1 N2
000 1
100 2
010 3
110 4
001 5
101 6
Xilinx Generic Interface (XGI) SuperClock Module www.xilinx.com 11
UG091 (v1.1) March 2, 2007
Functional Description
R
Figure 3 shows the output frequencies supported by the SuperClock module.
Table 5 lists examples of commonly used applications and the corresponding SuperClock
module configuration to achieve them. It introduces the user to the proper metrics
involved to achieve the desired output clock frequency range.
011 8
111 10
Table 4: N Divider Selection (Continued)
Inputs
N Divider Value
N0 N1 N2
Figure 3: Supported Output Frequencies
UG091_03_062305
100 200 300 50050 150
Output Frequency (MHz)
250 550
490.00-640.00
122.5-160.00
70.00-91.43
61.25-80.00
54.44-71.11
49.00-64.00
98.00-128.00
81.67-106.67
245.00-320.00
163.33-213.33
/
1
/
2
/
3
/
4
/
5
/
6
/
7
/
8
/
9
/
10
Table 5: Common Configurations
Input
Reference
Clock
M
Divider
N
Divider
VCO
(MHz)
Output
Frequency
(MHz)
Application
27 22 4 594 148.5 HDTV
22.4 25 4 560 140
24.75 24 4 594 148.5 HDTV
25 24 3 600 200
14.8351649 40 4 593.4066 148.351649 HDTV
19.44 32 4 622.08 155.52 SONET
19.44 32 4 622.08 155.52 SONET
19.44 32 1 622.08 622.08 SONET
12 www.xilinx.com Xilinx Generic Interface (XGI) SuperClock Module
UG091 (v1.1) March 2, 2007
Functional Description
R
The resultant output frequency is delivered by way of differential pair Q0 and NQ0 to a
1-to-4 differential LVDS fan-out buffer. This establishes three, 100Ω differential pair
outputs at CLK0, CLK1, and CLK2, and is A/C coupled to corresponding SMA pairs (J2,
J3), (J4, J5), and (J6, J7), respectively.
The REF_CLK output at SMA J8 is enabled when the reference clock output enable
(REF_OE) at J13 is pulled High or when a jumper is placed across pins 1 and 2 of J13. With
REF_OE enabled, the differential outputs are disabled. For normal operation, leave J13
open.
19.44 32 2 622.08 311.04 SONET
19.53125 32 4 625 156.25 10-Gigabit Ethernet
20 25 2 500 250 Ethernet, PCI Express
25 25 2 625 312.5 10-Gigabit Ethernet
25 25 5 625 125 1-Gigabit Ethernet
25 24 6 600 100 PCI Express
25 24 4 600 150 SATA
26.5625 24 6 637.5 106.25 Fibre Channel 1
26.5625 24 3 637.5 212.5 4-Gigabit Fibre Channel
26.5625 24 4 637.5 159.375 10-Gigabit Fibre Channel
31.25 18 3 562.5 187.5 12-Gigabit Ethernet
Notes: User Tips
1. REF_CLK * M divider value = VCO frequency
2. VCO Frequency / N Divider = Output frequency
Table 5: Common Configurations (Continued)
Input
Reference
Clock
M
Divider
N
Divider
VCO
(MHz)
Output
Frequency
(MHz)
Application
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

HW-XGI-SCLK-G

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Description:
MODULE SUPER CLOCK
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