10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
02/02/2012
IS61NLF102436A/IS61NVF102436A
IS61NLF204818A/IS61NVF204818A
READ/WRITE CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
6.5 7.5
Symbol Parameter Min. Max. Min. Max. Unit
fmax Clock Frequency — 133 — 117 MHz
tkc Cycle Time 7.5 — 8.5 — ns
tkh Clock High Time 2.2 — 2.5 — ns
tkl Clock Low Time 2.2 — 2.5 — ns
tkq Clock Access Time — 6.5 — 7.5 ns
tkqx
(2)
Clock High to Output Invalid 2.5 — 2.5 — ns
tkqlZ
(2,3)
Clock High to Output Low-Z 2.5 — 2.5 — ns
tkqhZ
(2,3)
Clock High to Output High-Z — 3.8 — 4.0 ns
toeq Output Enable to Output Valid — 3.2 — 3.4 ns
toelZ
(2,3)
Output Enable to Output Low-Z 0 — 0 — ns
toehZ
(2,3)
Output Disable to Output High-Z — 3.5 — 3.5 ns
tAs Address Setup Time 1.5 — 1.5 — ns
tws Read/Write Setup Time 1.5 — 1.5 — ns
tces Chip Enable Setup Time 1.5 — 1.5 — ns
tse Clock Enable Setup Time 1.5 — 1.5 — ns
tAdVs Address Advance Setup Time 1.5 — 1.5 — ns
tds Data Setup Time 1.5 — 1.5 — ns
tAh Address Hold Time 0.65 — 0.65 — ns
the Clock Enable Hold Time 0.5 — 0.5 — ns
twh Write Hold Time 0.5 — 0.5 — ns
tceh Chip Enable Hold Time 0.5 — 0.5 — ns
tAdVh Address Advance Hold Time 0.5 — 0.5 — ns
tdh Data Hold Time 0.5 — 0.5 — ns
tPds ZZ High to Power Down — 2 — 2 cyc
tPus ZZ Low to Power Down — 2 — 2 cyc
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
