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CD4538BC
Theory of Operation
FIGURE 2.
Trigger Operation
The block diagram of the CD4538BC is shown in Figure 1,
with circuit operation following.
As shown in Figure 1 and Figure 2, before an input trigger
occurs, the monostable is in the quiescent state with the Q
output low, and the timing capacitor C
X
completely charged
to V
DD
. When the trigger input A goes from V
SS
to V
DD
(while inputs B and C
D
are held to V
DD
) a valid trigger is
recognized, which turns on comparator C1 and N-Channel
transistor N1
(1)
. At the same time the output latch is set.
With transistor N1 on, the capacitor C
X
rapidly discharges
toward V
SS
until V
REF1
is reached. At this point the output
of comparator C1 changes state and transistor N1 turns off.
Comparator C1 then turns off while at the same time com-
parator C2 turns on. With transistor N1 off, the capacitor C
X
begins to charge through the timing resistor, R
X
, toward
V
DD
. When the voltage across C
X
equals V
REF2
, compara-
tor C2 changes state causing the output latch to reset (Q
goes low) while at the same time disabling comparator C2.
This ends the timing cycle with the monostable in the qui-
escent state, waiting for the next trigger.
A valid trigger is also recognized when trigger input B goes
from V
DD
to V
SS
(while input A is at V
SS
and input C
D
is at
V
DD
)
(2)
.
It should be noted that in the quiescent state C
X
is fully
charged to V
DD
, causing the current through resistor R
X
to
be zero. Both comparators are “off” with the total device
current due only to reverse junction leakages. An added
feature of the CD4538BC is that the output latch is set via
the input trigger without regard to the capacitor voltage.
Thus, propagation delay from trigger to Q is independent of
the value of C
X
, R
X
, or the duty cycle of the input wave-
form.
Retrigger Operation
The CD4538BC is retriggered if a valid trigger occurs
(3)
fol-
lowed by another valid trigger
(4)
before the Q output has
returned to the quiescent (zero) state. Any retrigger, after
the timing node voltage at pin 2 or 14 has begun to rise
from V
REF1
, but has not yet reached V
REF2
, will cause an
increase in output pulse width T. When a valid retrigger is
initiated
(4)
, the voltage at T2 will again drop to V
REF1
before
progressing along the RC charging curve toward V
DD
. The
Q output will remain high until time T, after the last valid
retrigger.
Reset Operation
The CD4538BC may be reset during the generation of the
output pulse. In the reset mode of operation, an input pulse
on C
D
sets the reset latch and causes the capacitor to be
fast charged to V
DD
by turning on transistor Q1
(5)
. When
the voltage on the capacitor reaches V
REF2
, the reset latch
will clear and then be ready to accept another pulse. If the
C
D
input is held low, any trigger inputs that occur will be
inhibited and the Q and Q
outputs of the output latch will
not change. Since the Q output is reset when an input low
level is detected on the C
D
input, the output pulse T can be
made significantly shorter than the minimum pulse width
specification.
