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9DB633AFILF

P1-P3P4-P6P7-P9P10-P12P13-P14
9DB633
IDT
®
Six Output Differential Buffer for PCIe Gen3 1668F—10/20/16
Six Output Differential Buffer for PCIe Gen3
1
DATASHEET
Recommended Application:
6 output PCIe Gen3 zero-delay/fanout buffer
General Description:
The 9DB633 zero-delay buffer supports PCIe Gen3
requirements, while being backwards compatible to PCIe
Gen2 and Gen1. The 9DB633 is driven by a differential SRC
output pair from an IDT 932S421 or 932SQ420 or equivalent
main clock generator. It attenuates jitter on the input clock
and has a selectable PLL bandwidth to maximize
performance in systems with or without Spread-Spectrum
clocking. An SMBus interface allows control of the PLL
bandwidth and bypass options, while 2 clock request (OE#)
pins make the 9DB633 suitable for Express Card
applications.
Key Specifications:
• Cycle-to-cycle jitter < 50 ps
• Output-to-output skew < 50 ps
• PCIe Gen3 phase jitter < 1.0ps RMS
Features/Benefits:
• OE# pins/Suitable for Express Card applications
• PLL or bypass mode/PLL can dejitter incoming clock
• Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL's
• Spread Spectrum Compatible/tracks spreading input
clock for low EMI
• SMBus Interface/unused outputs can be disabled
Output Features:
• 6 - 0.7V current mode differential HCSL output pairs
Block Diagram
SPREAD
COMPATIBLE
PLL
CONTROL
LOGIC
SMBDAT
SMBCLK
SRC_IN
SRC_IN#
PLL_BW
IREF
DIF1
DIF4
OE4#
OE1#
DIF(0,2,3,5)
IDT
®
Six Output Differential Buffer for PCIe Gen3 1668F—10/20/16
9DB633
Six Output Differential Buffer for PCIe Gen3
2
Datasheet
Power Distribution Table
Pin Configuration
VDD GND
7, 13, 16, 22 8,21 Differential Outputs
13 8 SMBus
N/A 27 IREF
28 27 Analog VDD & GND for PLL core
Description
Pin Number
PLL_BW 1 28 VDDA
SRC _IN 2 27 GNDA
SRC_IN# 3 26 IREF
vOE1# 4 25 vOE4#
DIF_0 5 24 DIF_5
DIF_ 0# 6 23 DIF_5#
VDD 7 22 VDD
GND 8 21 GND
DIF_1 9 20 DIF_4
DIF_ 1# 1 0 19 DIF_4#
DIF_2 11 18 DIF_3
DIF_ 2# 1 2 17 DIF_3#
VDD 13 16 VDD
SMBDAT
14 15 SMBCLK
9DB633
120K ohm pull down resistors
Note:
Pins preceeded by ' v ' have internal
IDT
®
Six Output Differential Buffer for PCIe Gen3 1668F—10/20/16
9DB633
Six Output Differential Buffer for PCIe Gen3
3
Datasheet
Pin Description
PIN # PIN NAME PIN TYPE DESCRIPT ION
1 PLL_BW IN
3.3V input for selecting PLL Band Width
0 = low
,
1= hi
g
h
2 SRC_IN IN 0.7 V Differential SRC TRUE in
p
ut
3 SRC_IN# IN 0.7 V Differential SRC COMPLEMENTARY input
4vOE1# IN
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
5DIF_
0
OUT 0.7V differential true clock out
p
u
t
6 DIF_0# OUT 0.7V differential Com
p
lementar
y
clock out
p
ut
7 VDD PWR Power su
pp
l
y,
nominal 3.3V
8 GND IN Ground pin.
9 DIF_1 OUT 0.7V differential true clock output
10 DIF_1# OUT 0.7V differential Complementary clock output
11 DIF_2 OUT 0.7V differential true clock out
p
u
t
12 D IF_2# OUT 0.7 V d iffe re ntia l C om
p
lementar
y
clock out
p
ut
13 VDD PWR Power su
pp
l
y,
nominal 3.3V
14 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant
15 SM BC LK IN C lo ck pi n o f SM BUS circu itr y, 5V tol er ant
16 VDD PWR Power supply, nominal 3.3V
17 D IF_3# OUT 0.7 V d iffe re ntia l C om
p
lementar
y
clock out
p
ut
18 D IF_
3
OUT 0.7V differential true clock out
p
u
t
19 D IF_4# OUT 0.7 V d iffe re ntia l C om
p
lementar
y
clock out
p
ut
20 DIF_4 OUT 0.7V differential true clock output
21 GND PWR Ground pin.
22 VDD PWR Power supply, nominal 3.3V
23 DIF_5# OUT 0.7V differential Complementary clock output
24 DIF_5 OUT 0.7V differential true clock out
p
u
t
25 v OE4 # IN
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
26 IR EF OUT
This pin establishes the reference for the differential current-mode output pairs. It
requires a fixed precision resistor to ground. 475ohm is the standard value for
100ohm differential impedance. Other impedances require different values. See
data sheet.
27 GNDA PWR Ground
p
in for the PLL core.
28 VDDA PWR 3.3V power for the PLL core.
Note:
Pins preceeded by ' v ' have inte rnal 120K ohm pull down resistors
P1-P3P4-P6P7-P9P10-P12P13-P14

9DB633AFILF

Mfr. #:
Buy 9DB633AFILF
Manufacturer:
IDT
Description:
Clock Buffer 4 OUTPUT PCIE GEN3 BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
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