9DB633AFLF Datasheet 9DB633AGILFT, 9DB633AGLFT, 9DB633AFILF | P7-P9

IDT

Six Output Differential Buffer for PCIe Gen3 1668F—10/20/16

9DB633

Six Output Differential Buffer for PCIe Gen3

Datasheet

HCSL Output Buffer

L1'

L2'

L4'

L3L3'

Rt Rt

PCI Express

Add-in Board

REF_CLK Input

Figure 2: PCI Express Connector Routing

Common Recommendations for Differential Routing Dimension or Value Unit Figure

L1 length, route as non-coupled 50ohm trace 0.5 max inch 1

L2 length, route as non-coupled 50ohm trace 0.2 max inch 1

L3 length, route as non-coupled 50ohm trace 0.2 max inch 1

Rs 33 ohm 1

Rt 49.9 ohm 1

Down Device Differential Routing

L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max inch 1

L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch 1

Differential Routing to PCI Express Connector

L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max inch 2

L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch 2

SRC Reference Clock

HCSL Output Buffer

L1'

L2'

L4'

L3L3'

Rt Rt

PCI Express

Down Device

REF_CLK Input

Figure 1: Down Device Routing

IDT

Six Output Differential Buffer for PCIe Gen3 1668F—10/20/16

9DB633

Six Output Differential Buffer for PCIe Gen3

Datasheet

Vdiff Vp-p Vcm R1 R2 R3 R4 Note

0.45v 0.22v 1.08 33 150 100 100

0.58 0.28 0.6 33 78.7 137 100

0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible

0.60 0.3 1.2 33 174 140 100 Standard LVDS

R1a = R1b = R1

R2a = R2b = R2

Alternative Termination for LVDS and other Common Differential Signals (figure 3)

HCSL Output Buffer

L1'

R1b

L2'

R1a

L4'

R2a R2b

Down Device

REF_CLK Input

Figure 3

L3'

R3 R4

Component Value Note

R5a, R5b 8.2K 5%

R6a, R6b 1K 5%

Cc 0.1 µF

Vcm 0.350 volts

Cable Connected AC Coupled Application (figure 4)

PCIe Device

REF_CLK Input

Figure 4

R5a

L4'

3.3 Volts

R5b

R6a R6b

IDT

Six Output Differential Buffer for PCIe Gen3 1668F—10/20/16

9DB633

Six Output Differential Buffer for PCIe Gen3

Datasheet

General SMBus serial interface information for the 9DB633

How to Write:

• Controller (host) sends a start bit.

• Controller (host) sends the write address D4

(H)

• ICS clock will

acknowledge

• Controller (host) sends the begining byte location = N

• ICS clock will

acknowledge

• Controller (host) sends the data byte count = X

• ICS clock will

acknowledge

• Controller (host) starts sending

Byte N through

Byte N + X -1

(see Note 2)

• ICS clock will

acknowledge

each byte

one at a time

• Controller (host) sends a Stop bit

How to Read:

• Controller (host) will send start bit.

• Controller (host) sends the write address D4

(H)

• ICS clock will

acknowledge

• Controller (host) sends the begining byte

location = N

• ICS clock will

acknowledge

• Controller (host) will send a separate start bit.

• Controller (host) sends the read address D5

(H)

• ICS clock will

acknowledge

• ICS clock will send the data byte count = X

• ICS clock sends

Byte N + X -1

• ICS clock sends

Byte 0 through byte X (if X

(H)

was written to byte 8)

• Controller (host) will need to acknowledge each byte

• Controllor (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

ICS (Slave/Receiver)

ACK

Byte N + X - 1

Data Byte Count = X

Beginning Byte N

stoP bit

X Byte

Index Block Write Operation

Slave Address D4

(H)

Beginning Byte = N

WRite

starT bit

Controller (Host)

TstarT bit

WR WRite

RT Repeat starT

RD ReaD

Beginning Byte N

Byte N + X - 1

N Not acknowledge

PstoP bit

Slave Address D5

(H)

Index Block Read Operation

Slave Address D4

(H)

Beginning Byte = N

ACK

Data Byte Count = X

ACK

ICS (Slave/Receiver)

Controller (Host)

X Byte

ACK

P1-P3 P4-P6 P7-P9 P10-P12 P13-P14

9DB633AFLF

Mfr. #:

Buy 9DB633AFLF

Manufacturer:

IDT

Description:

Clock Buffer 4 OUTPUT PCIE GEN3 BUFFER

Lifecycle:

New from this manufacturer.

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9DB633AFLF

9DB633AFLF

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