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9DB633AGLFT

P1-P3P4-P6P7-P9P10-P12P13-P14
IDT
®
Six Output Differential Buffer for PCIe Gen3 1668F—10/20/16
9DB633
Six Output Differential Buffer for PCIe Gen3
4
Datasheet
Electrical Characteristics - Absolute Maximum Ratings
PARAMETER SYMBOL CONDITIONS
MIN TYP MAX
UNITS NOTES
3.3V Core Supply Voltage VDDA 4.6 V 1,2
3.3V Logic Supply Voltage VDD 4.6 V 1,2
Input Low Voltage V
IL
GND-0.5 V 1
Input High Voltage V
IH
Except for SMBus interface V
D
D
+0.5V V 1
Input High Voltage V
IHSMB
SMBus clock and data pins 5.5V V 1
Storage Temperature Ts -65 150
°
C
1
Junction Temperature Tj 125 °C 1
Input ESD protection
ESD prot Human Body Model 2000 V 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor guaranteed.
Electrical Characteristics - Input/Supply/Common Parameters
TA = T
CO M
or T
IND
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
T
COM
Commmercial range 0 70 °C 1
T
IND
Industrial range -40 85 °C 1
Input High Voltage V
IH
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
2V
DD
+ 0.3 V 1
Input Low Voltage V
IL
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
GND
- 0.3 0.8 V 1
I
IN
Single-ended inputs, V
IN
= GND, V
IN
= VDD -5 5 uA 1
I
INP
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down resistors
-200 200 uA 1
F
ibyp
V
DD
= 3.3 V, Bypass mode 10 110 MHz 2
F
ipll
V
DD
= 3.3 V, 100MHz PLL mode 33 100.00 110 MHz 2
Pin Inductance L
pin
7nH1
C
IN
Logic Inputs, except DIF_IN 1.5 5 pF 1
C
INDIF_IN
DIF_IN differential clock inputs 1.5 2.7 pF 1,4
C
OUT
Output pin capacitance 6 pF 1
Clk Stabilization T
STAB
From V
DD
Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
1.8 ms 1,2
Input SS Modulation
Frequency
f
MODI N
Allowable Frequency
(Triangular Modulation)
30 33 kHz 1
OE# Latency t
LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
1 3 cycles 1,3
Tdrive_PD# t
DRVPD
DIF output enable after
PD# de-assertion
300 us 1,3
Tfall t
F
Fall time of control inputs 5 ns 1,2
Trise t
R
Rise time of control inputs 5 ns 1,2
SMBus Input Low Voltage V
ILSMB
0.8 V 1
SMBus Input High Voltage V
IHSMB
2.1 V
DDSMB
V1
SMBus Output Low Voltage V
OLSMB
@ I
PULLUP
0.4 V 1
SMBus Sink Current I
PULLUP
@ V
OL
4mA1
Nominal Bus Voltage V
DDSMB
3V to 5V +/- 10% 2.7 5.5 V 1
SCLK/SDATA Rise Time t
RSMB
(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA Fall Time t
FSMB
(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
SMBus Operating
Frequency
f
MAXSMB
Maximum SMBus operating frequency 100 kHz 1,5
1
Guaranteed by design and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swing.
5
The differential in
p
ut clock must be runnin
g
for the SMBus to be active
Ambient Operating
Temperature
Input Current
3
Time from deassertion until out
p
uts are >200 mV
4
DIF_IN input
Capacitance
Input Frequency
IDT
®
Six Output Differential Buffer for PCIe Gen3 1668F—10/20/16
9DB633
Six Output Differential Buffer for PCIe Gen3
5
Datasheet
Electrical Characteristics - DIF 0.7V Current Mode Differential Outputs
T
A
= T
COM
or T
IND;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Slew rate Trf Sco
p
e avera
g
in
g
on 0.6 2.5 4
V/ns
1, 2, 3
Slew rate matchin
g
Trf
Slew rate matchin
g
, Sco
p
e avera
g
in
g
on 9.5 20
%
1, 2, 4
Voltage High VHigh 660 740 850 1
Voltage Low VLow -150 8 150 1
Max Volta
g
e Vmax 760 1150 1
Min Volta
g
e Vmin -300 -3 1
Vswin
g
Vswin
g
Sco
p
e avera
g
in
g
off 300 1506 mV 1, 2
Crossin
g
Volta
g
e
(
abs
)
Vcross_abs Sco
p
e avera
g
in
g
off 250 378 550 mV 1, 5
Crossing Voltage (var)
-Vcross Scope averaging off 54 140 mV 1, 6
2
Measured from differential waveform
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross absolute)
allowed. The intent is to limit Vcross induced modulation b
y
settin
g
V_cross_delta to be smaller than V_cross absolute.
mV
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope averaging
on)
Measurement on single ended signal using absolute
value. (Scope averaging off)
mV
1
Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xR
R
). For R
R
= 475Ω (1%), I
REF
= 2.32mA. I
OH
=
6 x I
REF
and V
OH
= 0.7V @ Z
O
=50Ω (100
differential impedance).
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the
average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e.
Clock rising and Clock# falling).
Electrical Characteristics - Current Consumption
TA = T
COM
or T
IND
;
Su
pp
l
y
Volta
g
e VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Operating Supply Current I
DD3.3OP
All outputs active @100MHz, C
L
= Full load;
134 150
mA 1
I
DD3 .3P D
All diff pairs driven N/A mA
1
I
DD3. 3PDZ
All differential pairs tri-stated N/A mA
1
1
Guaranteed b
y
desi
g
n and characterization, not 100% tested in
p
roduction.
Powerdown Current
Electrical Characteristics - DIF_IN Clock Input Parameters
T
AMB
=T
COM
or T
IND
unless otherwise indicated, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input Crossover Voltage -
DIF_IN
V
CROSS
Cross Over Voltage 150 375 900 mV 1
Input Swing - DIF_IN V
SWING
Differential value 300 mV 1
Input Slew Rate - DIF_IN dv/dt Measured differentially 1 8 V/ns 1,2
Input Leakage Current I
IN
V
IN
= V
DD ,
V
IN
=
GND -5 5 uA
Input Duty Cycle d
tin
Measurement from differential wavefrom 45 55 % 1
Input Jitter - Cycle to Cycle J
DI FI n
Differential Measurement 0 125 ps 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured through +/-75mV window centered around differential zero
IDT
®
Six Output Differential Buffer for PCIe Gen3 1668F—10/20/16
9DB633
Six Output Differential Buffer for PCIe Gen3
6
Datasheet
Electrical Characteristics - Output Duty Cycle, Jitter, Skew and PLL Characterisitics
TA = T
COM
or T
IND;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
-3dB
p
oint in Hi
g
h BW Mode 2 2.3 4 MHz 1
-3dB
p
oint in Low BW Mode 0.4 0.5 1 MHz 1
PLL Jitter Peaking t
JPEAK
Peak Pass band Gain 1 2 dB 1
Duty Cycle t
DC
Measured differentially, PLL Mode 45 48 55 % 1
Duty Cycle Distortion t
DCD
Measured differentially, Bypass Mode @100MHz -2 1 2 % 1,4
t
p
dBYP
Bypass Mode, V
T
= 50% 2500 3660 4500 ps 1
t
p
dPLL
Hi BW PLL Mode V
T
= 50% -250 0 250 ps 1
Skew, Output to Output t
sk3
V
T
= 50% 15 50 ps 1
PLL mode 40 50
p
s1,3
Additive Jitter in Bypass Mode 10 50 ps 1,3
1
Guaranteed b
y
desi
g
n and characterization, not 100% tested in
p
roduction.
2
I
RE
F
= V
DD
/
(
3xR
R
)
. For R
R
= 475
Ω
(
1%
)
, I
REF
= 2.32mA. I
OH
= 6 x I
RE
F
and V
OH
= 0.7V @ Z
O
=50
Ω
.
3
Measured from differential waveform
4
Dut
y
c
y
cle distortion is the difference in dut
y
c
y
cle between the out
p
ut and the in
p
ut clock when the device is o
p
erated in b
yp
ass mode.
Skew, Input to Output
Jitter, Cycle to cycle t
jcyc-cyc
PLL Bandwidth BW
Electrical Characteristics - PCIe Phase Jitter Parameters
TA = T
COM
or T
IND;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
t
jp
hPCIeG1
PCIe Gen 1 32 86 ps (p-p) 1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
1.1 3
ps
(
rms
)
1,2
PCIe Gen 2 High Band
1.5MHz < f < N
yq
uist
(
50MHz
)
2.3
3.1
ps
(
rms
)
1,2
t
jphPCIeG3
PCIe Gen 3
(
PLL BW of 2-4MHz, CDR = 10MHz
)
0.5
1
ps
(
rms
)
1,2,4
t
jphPCIeG1
PCIe Gen 1 2 5 ps (p-p) 1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.2 0.3
ps
(
rms
)
1,2
PCIe Gen 2 High Band
1.5MHz < f < N
yq
uist
(
50MHz
)
0.8
1
ps
(
rms
)
1,2
t
jphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
0.1
0.2
ps
(rms)
1,2,4
1
A
pp
lies to all out
p
uts.
3
Sam
p
le size of at least 100K c
y
cles. This fi
g
ures extra
p
olates to 108
p
s
p
k-
p
k @ 1M c
y
cles for a BER of 1-12.
4
Sub
j
ect to final radification b
y
PCI SIG.
t
jphPCIeG2
2
See htt
p
://www.
p
cisi
g
.com for com
p
lete s
p
ecs
t
jphPCIeG2
Phase Jitter, PLL Mode
Additive Phase Jitter,
Bypass Mode
P1-P3P4-P6P7-P9P10-P12P13-P14

9DB633AGLFT

Mfr. #:
Buy 9DB633AGLFT
Manufacturer:
IDT
Description:
Clock Buffer 4 OUTPUT PCIE GEN3 BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
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