AD2S83
–15–
REV. E
Ripple Content
Ripple content is due to several factors. Tachogenerators suffer
from ripple due to the speed of rotation, commutator segments
and the number of poles. The resolver/RDC combination has a
predominant ripple at twice the resolver reference as a result of
the synchronous demodulator and at a frequency twice per
revolution due to the resolver windings mismatch.
Motor torque pulsations which are a consequence of excessive
velocity ripple have a detrimental effect upon the quality of
speed control in servo systems.
The resultant cogging effect will be particularly noticeable at
low speed and when the motor is in the low torque region.
Other undesirable side effects such as the increase in acoustic
noise from a motor and a temperature rise in the motor stator
windings are possible results of the presence of torque ripple.
For more detailed information of the causes and sources of
errors see the Velocity Errors section.
AD2S83 COMPARISON WITH DC TACHOGENERATOR
Comparative tests of the AD2S83 and a dc tachogenerator were
carried out. The tachogenerator was connected at the nondrive
end of the motor shaft with the resolver located behind the drive
shaft of the motor. The AD2S83 was located remotely. The
AD2S83 was set up with a 200 Hz bandwidth, reference fre-
quency of 2.6 kHz and resolution of 14 bits.
The comparative analysis can be summarized:
AD2S83 DC Tacho Conditions
Linearity % 0.1 0.1 03600 rpm
Reversion Error % FSO 0.3 0.25
Note the typical operating range of dc tachogenerator is
0 rpm-3600 rpm. The resolver/AD2S83 combination will oper-
ate up to speeds in excess of 10000 rpm.
Ripple Effects
The comparative analysis of the output ripple from the tacho-
generator and the AD2S83 is illustrated below.
Minimization of the AD2S83 output ripple is discussed in detail
in the Velocity Errors section.
Other Factors
Other factors concerning choice of feedback source have to be
addressed. On average the MTBF of a tachogenerator is 347
days as opposed to typically 8 years for a resolver. Resolvers are
relatively insensitive to temperature whereas a tachogenerator
will be specified up to a maximum of 100°C with a ±0.1%/°C
(above 25°C) degradation in output voltage. The brushless
resolver requires no preventative maintenance; the brushes on a
tachogenerator, however, will require periodic checking.
ACCELERATION ERROR
A tracking converter employing a Type 2 servo loop does not
suffer any velocity lag, however, there is an additional error due
to acceleration. This additional error can be defined using the
acceleration constant K
A
of the converter.
K
A
=
Input Acceleration
Error in Output Angle
The numerator and denominator must have consistent angular
units. For example if K
A
is in sec
2
, then the input acceleration
may be specified in degrees/sec
2
and the error output in degrees.
K
A
does not define maximum input acceleration, only the error due
to acceleration. The maximum acceleration allowable before the
converter loses track is dependent on the angular accuracy
requirements of the system.
Angular Accuracy × K
A
= Degrees/sec
2
K
A
can be used to predict the output position error for a
given input acceleration. For example for an acceleration of
100 revs/sec
2
, K
A
= 2.7 × 10
6
sec
2
and 12-bit resolution.
Error in LSBs =
Input acceleration [LSB/sec
2
]
K
A
[sec
2
]
=
100 [rev /sec
2
] × 2
12
2. 7 ×10
6
= 0.15 LSBs or 47.5 seconds of arc
To determine the value of K
A
based on the passive components
used to define the dynamics of the converter the following
should be used.
K
A
=
4.04 ×10
11
2
n
× R6 × R4 ×(C4 + C5)
Where n = resolution of the converter.
R4, R6 in ohms
C5, C4 in farads.
AD2S83
REV. E
–16–
SOURCES OF ERRORS
Integrator Offset
Additional inaccuracies in the conversion of the resolver signals
will result from an offset at the input to the integrator. This
offset will be treated as an error signal. The resulting angular
error will typically be 1 arc minute over the operating tempera-
ture range.
A description of how to adjust the zero offset is given in the
Component Selection section; the circuit required is shown in
Figure 1.
Differential Phase Shift
Phase shift between the sine and cosine signals from the resolver
is known as differential phase shift and can cause static error.
Some differential phase shift will be present on all resolvers as a
result of coupling. A small resolver residual voltage (quadrature
voltage) indicates a small differential phase shift. Additional
phase shift can be introduced if the sine channel wires and the
cosine channel wires are treated differently. For instance, differ-
ent cable lengths or different loads could cause differential phase
shift.
The additional error caused by differential phase shift on the
input signals approximates to
Error = 0.53 a × b arc minutes
where a = differential phase shift (degrees).
b = signal to reference phase shift (degrees).
This error can be minimized by choosing a resolver with a small
residual voltage, ensuring that the sine and cosine signals are
handled identically and removing the reference phase shift (see
the Connecting the Resolver section). By taking these precau-
tions the extra error can be made insignificant.
Most resolvers exhibit a phase shift between the signal and the
reference. This phase shift will, however, give rise under
dynamic conditions to an additional error defined by:
Shaft Speed (rps) × Phase Shift (Degrees )
Reference Frequency
= Error Degrees
Under static operating conditions phase shift between the refer-
ence and the signal lines alone will not theoretically affect the
converters static accuracy.
For example, for a phase shift of 20 degrees, a shaft rotation of
22 rps and a reference frequency of 5 kHz, the converter will
exhibit an additional error of:
22 × 20
5000
= 0.088 Degrees
This effect can be eliminated by placing a phase shift in the
reference to the converter equivalent to the phase shift in the
resolver (see the Connecting the Resolver section).
Note: Capacitive and inductive crosstalk in the signal and reference
leads and wiring can cause similar problems.
VELOCITY ERRORS
Some ripple or noise will always be present in the velocity
signal. Velocity signal ripple is caused by, or related to, the
following parameters. The resulting effects are generally addi-
tive. This means diagnosis needs to be an iterative process in
order to define the source of the error.
1.0 Reference Frequency
A ripple content at the reference frequency is superimposed
on the velocity signal output. The amplitude depends on
the loop bandwidth. This error is a function of a dc offset at
the input to Phase Sensitive Demodulator (PSD).
2.0 Resolver Inaccuracies
Impedance mismatch occur in the sine and cosine windings
of the resolver. These give rise to differential phase shift
between the sine and cosine inputs to the RDC and varia-
tions in the resolver output amplitudes.
2.1 Sine and Cosine Amplitude Mismatch
This is normally identified by the presence of asymmetrical
ripple voltages.
2.2 Differential Phase Shift between the Sine and Cosine Inputs
The frequency of this ripple is usually twice the input veloc-
ity, and the amplitude is proportional to the magnitude of
the velocity signal. The phase shift is normally induced
through the connections from the resolver to the converter.
Maintaining equal lengths of screened twisted pair cable
from the resolver to the AD2S83 will reduce the effects of
resistive imbalance, and therefore, reduce differential phase
shift.
3.0 LSB Update Ripple
LSB update noise occurs as the resolver rotates and the
digital outputs of the RDC are updated. For a correctly
scaled loop, this ripple component has a magnitude of
approximately 2 mV peak at 16-bit resolution.
3.1 Ripple due to the LSB rate given by:
LSB rate = N × Reference Frequency
The PSD generates sums and differences of all its compo-
nent input frequencies, so when the LSB update rate is an
multiple of the reference frequency, a beat frequency is
generated. The magnitude of this ripple is a function of the
LSB weighting, i.e., ripple is less at 16 bits.
4.0 Torque Ripple
Torque ripple is a phenomenon associated with motors. An
ac motor naturally exhibits a sinusoidal back emf. In an
ideal system the current fed to the motor should, in order
to cancel, also be sinusoidal. In practice the current is often
trapezoidal. Consequently, the output torque from the motor
will not be smooth and torque ripple is created. If the load-
ing on a motor is constant, the velocity of the motor shaft
will vary as a result of the cyclic variation of motor torque.
The variation in velocity then appears on the velocity
output as ripple. This is not an error but a true velocity
variation in the system.
AD2S83
–17–
REV. E
Offset Errors
The limiting factor in the measuring of low or creep speeds is
the level of dc offset present at zero velocity. The zero velocity
dc offset at the output of the AD2S83 is a function of the input
bias current to the VCO and the value for the input resistor R6.
See Circuit Functions and Dynamic Performance VCO.
The offset can be minimized by reducing the maximum tracking
rate so reducing the value for R6. Offset is a function of tracking
rate and therefore resolution; the dc offset is lowest at 16 bits.
To increase the dynamic range of the velocity dynamic resolu-
tion switching can be employed. (Contact MCG Applications
for more information.)
CONNECTING THE RESOLVER
The recommended connection circuit is shown in Figure 11.
In cases where the reference phase relative to the input signals
from the resolver requires adjustment, this can be easily
achieved by varying the value of the resistor R2 of the HF filter
(see Figure 1).
Assume that R1 = R2 = R and C1 = C2 = C
and Reference Frequency =
1
2 π RC
.
By altering the value of R2, the phase of the reference relative to
the input signals will change in an approximately linear manner
for phase shifts of up to 10 degrees.
Increasing R2 by 10% introduces a phase lag of two degrees.
Decreasing R2 by 10% introduces a phase lead of two degrees.
R9
1M
R8
4.7M
R2
15k
R4
130k
R6
62k
R5
200k
R7
3.3k
R3
100k
C3
100nF
100nF
C2
2.2nF
C7
150pF
C4
1.2nF
C6
390pF
C5
6.2nF
100nF
VELOCITY
O/P
12V
0V
COS LOW
REF LOW
COS HIGH
SIN LOW
SIN HIGH
+12V
REFERENCE
INPUT
RESOLVER
SIGNAL
MSB
+5V
ENABLE
LSB
BYTE
SELECT
INHIBIT
SC2
DATA LOAD
BUSY
RIPPLE CLOCK
COMPLEMENT
DIRECTION
NOTE: R7, C6 AND C7 SHOULD BE CONNECTED AS
CLOSE AS POSSIBLE TO THE CONVERTER PINS.
SIGNAL SCREENS SHOULD BE CONNECTED TO PIN 5.
6543214443424140
18 19 20 21 22 23 24 25 26 27 28
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
AD2S83
TOP VIEW
(Not to Scale)
DATA
OUTPUT
DATA OUTPUT
R1
15k
C1
2.2nF
Figure 11. Typical Circuit Configuration
C
R
PHASE LEAD = ARC TAN
1
2fRC
R
C
PHASE LAG = ARC TAN 2fRC
PHASE SHIFT
CIRCUITS
Figure 10. Phase Shift Circuits
TYPICAL CIRCUIT CONFIGURATION
Figure 11 shows a typical circuit configuration for the AD2S83
with 12-bit resolution. Values of the external components have
been chosen for a reference frequency of 5 kHz and a maximum
tracking rate of 260 rps with a bandwidth of 520 Hz. Placing the
values for R4, R6, C4, and C5 in the equation for K
A
gives a
value of 1.65 × 10
6
. The resistors are 0.125 W, 5% tolerance
preferred values. The capacitors are 100 V ceramic, 10% toler-
ance components.
For signal and reference voltages greater than 2 V rms a simple
voltage divider circuit of resistors can be used to generate the
correct signal level at the converter. Care should be taken to
ensure that the ratios of the resistors between the sine signal line
and ground and the cosine signal line and ground are the same.
Any difference will result in an additional position error.
For more information on resistive scaling of SIN, COS, and
REFERENCE converter inputs refer to the application note,
Circuit Applications of the 2S81 and 2S80 Resolver-to-Digital
Converters.

AD2S83APZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized IC Var Resolution R/D Converter
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet