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A3983SLPTR-T

P1-P3P4-P6P7-P9P10-P12P13-P13
DMOS Microstepping Driver with Translator
A3983
10
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Full
Step
#
Half
Step
#
1/4
Step
#
1/8
Step
#
Phase 1
Current
[% I
tripMax
]
(%)
Phase 2
Current
[% I
tripMax
]
(%)
Step
Angle
(º)
1 1 1 100.00 0.00 0.0
2 98.08 19.51 11.3
2 3 92.39 38.27 22.5
4 83.15 55.56 33.8
123570.71 70.71 45.0
6 55.56 83.15 56.3
4 7 38.27 92.39 67.5
8 19.51 98.08 78.8
3 5 9 0.00 100.00 90.0
10 –19.51 98.08 101.3
6 11 –38.27 92.39 112.5
12 –55.56 83.15 123.8
2 4 7 13 –70.71 70.71 135.0
14 –83.15 55.56 146.3
8 15 –92.39 38.27 157.5
16 –98.08 19.51 168.8
5 9 17 –100.00 0.00 180.0
18 –98.08 –19.51 191.3
10 19 –92.39 –38.27 202.5
20 –83.15 –55.56 213.8
3 6 11 21 –70.71 –70.71 225.0
22 –55.56 –83.15 236.3
12 23 –38.27 –92.39 247.5
24 –19.51 –98.08 258.8
7 13 25 0.00 –100.00 270.0
26 19.51 –98.08 281.3
14 27 38.27 –92.39 292.5
28 55.56 –83.15 303.8
4 8 15 29 70.71 –70.71 315.0
30 83.15 –55.56 326.3
16 31 92.39 –38.27 337.5
32 98.08 –19.51 348.8
Table 2. Step Sequencing Settings
Home microstep position at Step Angle 45º; DIR = H
DMOS Microstepping Driver with Translator
A3983
11
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Terminal List Table
Name
Number
Description
Package LP
CP1 1 Charge pump capacitor terminal
CP2 2 Charge pump capacitor terminal
VCP 3 Reservoir capacitor terminal
VREG 4 Regulator decoupling terminal
MS1 5 Logic input
MS2 6 Logic input
RESET 7 Logic input
ROSC 8 Timing set
SLEEP 9 Logic input
VDD 10 Logic supply
STEP 11 Logic input
REF 12 G
m
reference voltage input
GND 13, 24 Ground*
DIR 14 Logic input
OUT1B 15 DMOS Full Bridge 1 Output B
VBB1 16 Load supply
SENSE1 17 Sense resistor terminal for Bridge 1
OUT1A 18 DMOS Full Bridge 1 Output A
OUT2A 19 DMOS Full Bridge 2 Output A
SENSE2 20 Sense resistor terminal for Bridge 2
VBB2 21 Load supply
OUT2B 22 DMOS Full Bridge 2 Output B
ENABLE 23 Logic input
NC – No connection
PAD – Exposed pad for enhanced thermal dissipation*
*The GND pins must be tied together externally by connecting to the PAD ground plane
under the device.
Package LP
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
CP1
CP2
VCP
VREG
MS1
MS2
RESET
ROSC
SLEEP
VDD
STEP
REF
GND
ENABLE
OUT2B
VBB2
SENSE2
GND
OUT2A
OUT1A
SENSE1
VBB1
OUT1B
DIR
PAD
DMOS Microstepping Driver with Translator
A3983
12
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
LP Package, 24-Pin TSSOP with Exposed Thermal Pad
1.20 MAX
C
SEATING
PLANE
0.15 MAX
C0.10
24X
0.65
6.103.00
4.32
1.65
0.45
0.65
0.25
21
24
3.00
4.32
(1.00)
GAUGE PLANE
SEATING PLANE
B
A
A
Terminal #1 mark area
B
For reference only
(reference JEDEC MO-153 ADT)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Reference land pattern layout (reference IPC7351
TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all
adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a multilayer
PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
PCB Layout Reference View
Exposed thermal pad (bottom surface)
C
C
7.80 ±0.10
4.40 ±0.10 6.40 ±0.20
0.60 ±0.15
4° ±4
0.25
+0.05
–0.06
0.15
+0.05
–0.06
P1-P3P4-P6P7-P9P10-P12P13-P13

A3983SLPTR-T

Mfr. #:
Buy A3983SLPTR-T
Manufacturer:
Description:
DMOS Stepper Motor Driver 24-Pin TSSOP EP T/R
Lifecycle:
New from this manufacturer.
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