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ISL8843AUZ

P1-P3P4-P6P7-P9P10-P12P13-P13
7
FN9238.2
September 14, 2015
Pin Descriptions
RTCT - This is the oscillator timing control pin. The
operational frequency and maximum duty cycle are set by
connecting a resistor, RT, between VREF and this pin and a
timing capacitor, CT, from this pin to GND. The oscillator
produces a sawtooth waveform with a programmable
frequency range up to 2.0MHz. The charge time, T
C
, the
discharge time, T
D
, the switching frequency, f, and the
maximum duty cycle, Dmax, can be approximated from the
following equations:
The formulae have increased error at higher frequencies due
to propagation delays. Figure 4 may be used as a guideline
in selecting the capacitor and resistor values required for a
given frequency.
COMP - COMP is the output of the error amplifier and the
input of the PWM comparator. The control loop frequency
compensation network is connected between the COMP and
FB pins.
FB - The output voltage feedback is connected to the
inverting input of the error amplifier through this pin. The
non-inverting input of the error amplifier is internally tied to a
reference voltage.
CS - This is the current sense input to the PWM comparator.
The range of the input signal is nominally 0 to 1.0V and has
an internal offset of 100mV.
GND - GND is the power and small signal reference ground
for all functions.
Typical Performance Curves
FIGURE 1. FREQUENCY vs TEMPERATURE FIGURE 2. REFERENCE VOLTAGE vs TEMPERATURE
FIGURE 3. EA REFERENCE vs TEMPERATURE FIGURE 4. RTCT vs FREQUENCY
-60 -40 -20 0 20 40 60 80 100 120 140
0.98
0.99
1
1.01
TEMPERATURE (°C)
NORMALIZED FREQUENCY
-60 -40 -20 0 20 40 60 80 100
0.995
0.996
0.997
0.998
0.999
1.000
1.001
TEMPERATURE (°C)
NORMALIZED VREF
140120
-60 -40 -20 0 20 40 60 80 100 120 140
0.996
0.997
0.998
1.000
1.001
TEMPERATURE (°C)
NORMALIZED EA REFERENCE
1 10 100
1
10
100
1•10
3
RT (k)
FREQUENCY (kHz)
CT =
100pF
220pF
330pF
470pF
1.0nF
2.2nF
3.3nF
4.7nF
6.8nF
T
C
0.533 RT CT
(EQ. 1)
T
D
RT– CT
0.008 RT 3.83–
0.008 RT 1.71–
----------------------------------------------


ln
(EQ. 2)
f 1T
C
T
D
+=
(EQ. 3)
DT
C
f=
(EQ. 4)
ISL8843
8
FN9238.2
September 14, 2015
OUT - This is the drive output to the power switching device.
It is a high current output capable of driving the gate of a
power MOSFET with peak currents of 1.0A. This GATE
output is actively held low when V
DD
is below the UVLO
threshold.
V
DD
- V
DD
is the power connection for the device. The total
supply current will depend on the load applied to OUT. Total
I
DD
current is the sum of the operating current and the
average output current. Knowing the operating frequency, f,
and the MOSFET gate charge, Qg, the average output
current can be calculated from:
To optimize noise immunity, bypass V
DD
to GND with a
ceramic capacitor as close to the V
DD
and GND pins as
possible.
VREF - The 5.00V reference voltage output. +1.0/-1.5%
tolerance over line, load and operating temperature. Bypass
to GND with a 0.1F to 3.3F capacitor to filter this output as
needed.
Functional Description
Features
The ISL8843 current mode PWM makes an ideal choice for
low-cost flyback and forward topology applications. With its
greatly improved performance over industry standard parts,
it is the obvious choice for new designs or existing designs
which require updating.
Oscillator
The ISL8843 has a sawtooth oscillator with a programmable
frequency range to 2MHz, which can be programmed with a
resistor from VREF and a capacitor to GND on the RTCT
pin. (Please refer to Figure 4 for the resistor and capacitance
required for a given frequency.)
Soft-Start Operation
Soft-start must be implemented externally. One method,
illustrated below, clamps the voltage on COMP.
The COMP pin is clamped to the voltage on capacitor C1
plus a base-emitter junction by transistor Q1. C1 is charged
from VREF through resistor R1 and the base current of Q1.
At power-up C1 is fully discharged, COMP is at ~0.7V, and
the duty cycle is zero. As C1 charges, the voltage on COMP
increases, and the duty cycle increases in proportion to the
voltage on C1. When COMP reaches the steady state
operating point, the control loop takes over and soft start is
complete. C1 continues to charge up to VREF and no longer
affects COMP. During power down, diode D1 quickly
discharges C1 so that the soft start circuit is properly
initialized prior to the next power on sequence.
Gate Drive
The ISL8843 is capable of sourcing and sinking 1A peak
current. To limit the peak current through the IC, an optional
external resistor may be placed between the totem-pole
output of the IC (OUT pin) and the gate of the MOSFET. This
small series resistor also damps any oscillations caused by
the resonant tank of the parasitic inductances in the traces of
the board and the FET’s input capacitance.
Slope Compensation
For applications where the maximum duty cycle is less than
50%, slope compensation may be used to improve noise
immunity, particularly at lighter loads. The amount of slope
compensation required for noise immunity is determined
empirically, but is generally about 10% of the full scale
current feedback signal. For applications where the duty
cycle is greater than 50%, slope compensation is required to
prevent instability.
Slope compensation may be accomplished by summing an
external ramp with the current feedback signal or by
subtracting the external ramp from the voltage feedback
error signal. Adding the external ramp to the current
feedback signal is the more popular method.
From the small signal current-mode model [1] it can be
shown that the naturally-sampled modulator gain, Fm,
without slope compensation, is
where Sn is the slope of the sawtooth signal and Tsw is the
duration of the half-cycle. When an external ramp is added,
the modulator gain becomes
where Se is slope of the external ramp and
The criteria for determining the correct amount of external
ramp can be determined by appropriately setting the
damping factor of the double-pole located at the switching
I
OUT
Qg f=
(EQ. 5)
FIGURE 5. SOFT-START
VREF
COMP
GND
ISL8843
C1
Q1
D1 R1
Fm
1
SnTsw
--------------------
=
(EQ. 6)
m
c
1
Se
Sn
-------
+=
(EQ. 8)
ISL8843
9
FN9238.2
September 14, 2015
frequency. The double-pole will be critically damped if the
Q-factor is set to 1, over-damped for Q < 1, and under-
damped for Q > 1. An under-damped condition may result in
current loop instability.
where D is the percent of on time during a switching cycle.
Setting Q = 1 and solving for Se yields
Since Sn and Se are the on time slopes of the current ramp
and the external ramp, respectively, they can be multiplied
by Ton to obtain the voltage change that occurs during Ton.
where Vn is the change in the current feedback signal (I)
during the on time and Ve is the voltage that must be added
by the external ramp.
For a flyback converter, Vn can be solved for in terms of
input voltage, current transducer components, and primary
inductance, yielding
where R
CS
is the current sense resistor, T
SW
is the
switching frequency, L
p
is the primary inductance, V
IN
is the
minimum input voltage, and D is the maximum duty cycle.
The current sense signal at the end of the ON time for CCM
operation is:
where V
CS
is the voltage across the current sense resistor,
L
s
is the secondary winding inductance, and I
O
is the output
current at current limit. Equation 13 assumes the voltage
drop across the output rectifier is negligible.
Since the peak current limit threshold is 1.00V, the total
current feedback signal plus the external ramp voltage must
sum to this value when the output load is at the current limit
threshold.
Substituting Equations 12 and 13 into Equation 14 and
solving for R
CS
yields
Adding slope compensation is accomplished in the ISL8843
using an external buffer transistor and the RTCT signal. A
typical application sums the buffered RTCT signal with the
current sense feedback and applies the result to the CS pin
as shown in Figure 6.
Assuming the designer has selected values for the RC filter
(R6 and C4) placed on the CS pin, the value of R9 required
to add the appropriate external ramp can be found by
superposition.
The factor of 2.05 in Equation 16 arises from the peak
amplitude of the sawtooth waveform on RTCT minus a base-
emitter junction drop. That voltage multiplied by the
maximum duty cycle is the voltage source for the slope
compensation. Rearranging to solve for R9 yields:
The value of R
CS
determined in Equation 15 must be
rescaled so that the current sense signal presented at the
CS pin is that predicted by Equation 13. The divider created
by R6 and R9 makes this necessary.
Q
1
m
c
1D–0.5–
-------------------------------------------------
=
(EQ. 9)
V
e
V
n
1
---
0.5+


1
1D–
-------------
1–


=
(EQ. 11)
V
e
DT
SW
V
IN
R
CS

L
p
----------------------------------------------------
1
---
0.5+


1
1D–
-------------
1–


= V
(EQ. 12)
V
CS
N
S
R
CS
N
P
------------------------
I
O
1D–V
O
T
sw
2L
s
----------------------------------------------
+



= V (EQ. 13)
V
e
V
CS
+ 1=
(EQ. 14)
R
CS
1
DT
sw
V
IN

L
p
---------------------------------
1
---
0.5+
1D–
------------------
1–




N
s
N
p
-------
I
O
1D–V
O
T
sw

2L
s
----------------------------------------------
+



+
---------------------------------------------------------------------------------------------------------------------------------------------------------
=
(EQ. 15)
FIGURE 6. SLOPE COMPENSATION
CS
RTCT
R6
C4
R9
ISL8843
VREF
V
e
2.05D R6
R6 R9+
-----------------------------
= V
(EQ. 16)
R9
2.05D V
e
–R6
V
e
-----------------------------------------------
=
(EQ. 17)
R
CS
R6 R9+
R9
----------------------
R
CS
=
(EQ. 18)
ISL8843
P1-P3P4-P6P7-P9P10-P12P13-P13

ISL8843AUZ

Mfr. #:
Buy ISL8843AUZ
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers W/ANL CUR MODE PWM 100%DC 8 4V UVLO 8LD
Lifecycle:
New from this manufacturer.
Delivery:
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