NB7L14
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4
Table 4. DC CHARACTERISTICS, MULTI−LEVEL INPUTS V
CC
= 2.375 V to 3.6V, GND = 0 V, T
A
= −40°C to +85°C
Symbol
Characteristic Min Typ Max Unit
POWER SUPPLY CURRENT
V
CC
Power Supply Voltage V
CC
= 2.5 V
V
CC
= 3.3 V
2.375
3.0
2.5
3.3
2.625
3.6
V
I
CC
Power Supply Current (Inputs and Outputs Open) 85 105 mA
LVPECL OUTPUTS (Notes 5 & 6)
V
OH
Output HIGH Voltage
V
CC
= 2.5V
V
CC
= 3.3V
V
CC
– 1145
1355
2155
V
CC
– 900
1600
2400
V
CC
– 825
1675
2475
mV
V
OL
Output LOW Voltage
V
CC
= 2.5 V
V
CC
= 3.3 V
V
CC
– 2000
500
1300
V
CC
– 1700
800
1600
V
CC
– 1500
1000
1800
mV
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (see Figure 5 & 7) (Note 7)
V
IH
Single−ended Input HIGH Voltage V
th
+ 75 V
CC
mV
V
IL
Single−ended Input LOW Voltage GND V
th
− 75 mV
V
th
Input Threshold Reference Voltage Range (Note 8) 1125 V
CC
− 75 mV
V
ISE
Single−ended Input Voltage Amplitude (V
IH
− V
IL
) 150 2800 mV
VREFAC
V
REFAC
Output Reference Voltage (100 mA Load)
V
CC
− 1400 V
CC
− 1300 V
CC
− 1000 mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figure 6 & 8) (Note 9)
V
IHD
Differential Input HIGH Voltage 1200 V
CC
mV
V
ILD
Differential Input LOW Voltage 0 V
IHD
− 50 mV
V
ID
Differential Input Voltage (V
IHD
− V
ILD
) 100 2800 mV
V
CMR
Input Common Mode Range (Differential Configuration) (Note 10)
(Figure 9)
950 V
CC
− 50 mV
I
IH
Input HIGH Current IN / IN, (VT Open) −150 150
mA
I
IL
Input LOW Current IN / IN, (VT Open) −150 150
mA
TERMINATION RESISTORS
R
TIN
Internal Input Termination Resistor 45 50 55
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. LVPECL outputs loaded with 50 W to V
CC
− 2.0 V for proper operation.
6. Input and output parameters vary 1:1 with V
CC
.
7. V
th
, V
IH
, V
IL,,
and V
ISE
parameters must be complied with simultaneously.
8. V
th
is applied to the complementary input when operating in single−ended mode.
9. V
IHD
, V
ILD,
V
ID
and V
CMR
parameters must be complied with simultaneously.
10.V
MR
min varies 1:1 with V
EE
, V
CMR
max varies 1:1 with V
CC
. The V
CMR
range is referenced to the most positive side of the differential input
signal.
NB7L14
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5
Table 5. AC CHARACTERISTICS V
CC
= 2.375 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C ; (Note 11)
Symbol
Characteristic Min Typ Max Unit
f
MAX
Maximum Input Clock Frequency; V
OUT
w 400 mV 7 8 GHz
f
DATAMAX
Maximum Operating Data Rate; NRZ, (PRBS23) 10 11 Gbps
V
OUTPP
Output Voltage Amplitude (Note 15) f
in
v 5 GHz
(See Figure 9) f
in
7 GHz
500
400
720
450
mV
t
PLH
,
t
PHL
Propagation Delay IN to Q 125 165 200 ps
t
SKEW
Duty Cycle Skew (Note 12)
Output – Output Within Device Skew
Device to Device Skew
3
15
15
50
ps
t
DC
Output Clock Duty Cycle f
in
v 7 GHz
(Reference Duty Cycle = 50%)
45 50 55 %
t
JITTER
RMS Random Clock Jitter (Note 13) f
in
v 7 GHz
Peak−to−Peak Data Dependent Jitter (Note 14) f
in
v 10.7 Gb/s 0.5
5
0.8
15
ps rms
ps pk−pk
t
jit(
f
)
Additive RMS Phase Jitter
f
c
= 622.08 MHz, Integration Range: 12 kHz to 20 MHz (See Figure 17)
24 fs
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 15)
100 1200 mV
t
r
t
f
Output Rise/Fall Times @ 1.0 GHz Qx, Qx
(20% − 80%)
30 45 60 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured by forcing V
INPP
(min) from a 50% duty cycle clock source. All loading with an external R
L
= 50 W to V
CC
– 2.0 V. Input edge rates
40 ps (20% − 80%).
12.Skew is measured between outputs under identical transitions and conditions @ 0.5 GHz. Duty cycle skew is measured between differential
outputs using the deviations of the sum of T
pw
− and T
pw
+ @ 0.5 GHz.
13.Additive RMS jitter with 50% duty cycle clock signal.
14.Additive peak−to−peak data dependent jitter with input NRZ data at PRBS23.
15.Input and output voltage swing is a single−ended measurement operating in differential mode.
Figure 3. CLOCK Output Voltage Amplitude
(V
OUTPP
) vs. Input Frequency (f
in
) at Ambient
Temperature (Typ)
f
in
, Clock Input Frequency (GHz)
OUTPUT VOLTAGE AMPLITUDE
(mV)
800
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
Q AMP (mV)
Figure 4. Input Structure
50 W
50 W
V
T
V
CC
IN
IN
700
600
500
400
300
NB7L14
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6
IN
V
th
IN
V
th
Figure 5. Differential Input Driven
Single−Ended
V
IH
V
IL
V
IHmax
V
ILmax
V
IH
V
th
V
IL
V
IHmin
V
ILmin
V
CC
V
thmax
V
thmin
GND
V
th
IN
IN
V
ILDmax
V
IHDmax
V
IHDtyp
V
ILDtyp
V
IHDmin
V
ILDmin
V
CMR
GND
V
ID
= V
IHD
− V
ILD
V
CC
IN
IN
Q
Q
t
PLH
t
PHL
V
OUTPP
= V
OH
(Q) − V
OL
(Q)
V
INPP
= V
IH
(IN) − V
IL
(IN)
V
IHD
V
ILD
V
ID
= |V
IHD(IN)
− V
ILD(IN)|
IN
IN
Figure 6. Differential Inputs
Driven Differentially
Figure 7. V
th
Diagram Figure 8. Differential Inputs Driven Differentially
Figure 9. V
CMR
Diagram Figure 10. AC Reference Measurement
IN
IN
V
CMmax
V
CMmin

NB7L14MNTXG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Buffer TSMC1-4 MLL TO PECL
Lifecycle:
New from this manufacturer.
Delivery:
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