Integrated Synthesizer and VCO
Data Sheet
ADF4360-0
Rev. D Document Feedback
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FEATURES
Output frequency range: 2400 MHz to 2725 MHz
Divide-by-2 output
3.0 V to 3.6 V power supply
1.8 V logic compatibility
Integer-N synthesizer
Programmable dual-modulus prescaler 16/17, 32/33
Programmable output power level
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
APPLICATIONS
Wireless handsets (DECT, GSM, PCS, DCS, WCDMA)
Test equipment
Wireless LANs
CATV equipment
GENERAL DESCRIPTION
The ADF4360-0 is a fully integrated integer-N synthesizer and
voltage-controlled oscillator (VCO). The ADF4360-0 is designed
for a center frequency of 2600 MHz. In addition, a divide-by-2
option is available, whereby the user gets an RF output of
between 1200 MHz and 1360 MHz.
Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging
from 3.0 V to 3.6 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
MUXOUT
CP
V
VCO
REF
IN
CLK
DATA
LE
AV
DD
DV
DD
CE
AGND DGND CPGND
R
SET
V
TUNE
C
C
C
N
RF
OUT
A
RF
OUT
B
VCO
CORE
PHASE
COMPARATOR
MUTE
DIVSEL = 2
DIVSEL = 1
N = (BP + A)
LOAD
LOAD
CHARGE
PUMP
OUTPUT
STAGE
MULTIPLEXER
INTEGER
REGISTER
13-BIT B
COUNTER
14-BIT R
COUNTER
24-BIT
FUNCTION
LATCH
24-BIT
DATA REGISTER
5-BIT A
COUNTER
PRESCALER
P/P+1
MULTIPLEXER
LOCK
DETECT
÷2
ADF4360-0
04644-001
Figure 1.
ADF4360-0* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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EVALUATION KITS
ADF4360-0 Evaluation Board
DOCUMENTATION
Application Notes
AN-30: Ask the Applications Engineer - PLL Synthesizers
AN-873: Lock Detect on the ADF4xxx Family of PLL
Synthesizers
Data Sheet
ADF4360-0: Integrated Synthesizer and VCO Data Sheet
User Guides
UG-095: Evaluation Board User Guide for ADF4360-0
UG-476: PLL Software Installation Guide
SOFTWARE AND SYSTEMS REQUIREMENTS
ADF4360 - Microcontroller No-OS Driver
TOOLS AND SIMULATIONS
ADIsimPLL™
ADIsimRF
REFERENCE MATERIALS
Product Selection Guide
RF Source Booklet
Technical Articles
Phase Locked Loops for High-Frequency Receivers and
Transmitters – Part 1
Phase Locked Loops for High-Frequency Receivers and
Transmitters – Part 3
Phase-Locked Loops for High-Frequency Receivers and
Transmitters - Part 2
DESIGN RESOURCES
ADF4360-0 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
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SAMPLE AND BUY
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TECHNICAL SUPPORT
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number.
DOCUMENT FEEDBACK
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ADF4360-0 Data Sheet
Rev. D | Page 2 of 24
TABLE OF CONTENTS
Specifications ..................................................................................... 3
Timing Characteristics ..................................................................... 5
Absolute Maximum Ratings ............................................................ 6
Transistor Count ........................................................................... 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Circuit Description ........................................................................... 9
Reference Input Section ............................................................... 9
Prescaler (P/P + 1) ........................................................................ 9
A and B Counters ......................................................................... 9
R Counter ...................................................................................... 9
PFD and Charge Pump ................................................................ 9
MUXOUT and Lock Detect ...................................................... 10
Input Shift Register..................................................................... 10
VCO ............................................................................................. 10
Output Stage ................................................................................ 11
Latch Structure ........................................................................... 12
Power-Up ..................................................................................... 16
Control Latch .............................................................................. 18
N Counter Latch ......................................................................... 19
R Counter Latch ......................................................................... 19
Applications Information .............................................................. 20
Fixed Frequency LO ................................................................... 20
Interfacing ................................................................................... 20
PCB Design Guidelines for Chip Scale Package........................... 21
Output Matching ........................................................................ 21
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 22
REVISION HISTORY
3/16—Rev. C to Re v. D
Changed ADF4360 Family to ADF4360-0 and
ADSP-21xx to ADSP-2181 ........................................... Throughout
Changes to Figure 3 .......................................................................... 7
Updated Outline Dimensions ....................................................... 22
Changes to Ordering Guide .......................................................... 22
11/12—Rev. B to Rev. C
Changes to Table 1 ............................................................................ 4
Changes to Table 3 ............................................................................ 6
Change to Output Matching Section ........................................... 22
Updated Outline Dimensions ....................................................... 23
2/12—Rev. A to Rev. B
Changes to Figure 3 and Table 4 ..................................................... 7
Updated Outline Dimensions ....................................................... 22
Changes to Ordering Guide .......................................................... 22
12/04—Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Changes to Timing Characteristics ................................................. 5
Changes to Power-Up Section ...................................................... 16
Added Table 10 ............................................................................... 16
Added Figure 16 ............................................................................. 16
Changes to Ordering Guide .......................................................... 22
Updated Outline Dimensions ....................................................... 22
7/04—Revision 0: Initial Version

ADF4360-0BCPZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Phase Locked Loops - PLL Intg Integer-N VCO Out Freq 2400-2725
Lifecycle:
New from this manufacturer.
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