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DS1123LE-25+

P1-P3P4-P6P7-P9P10-P12P13-P14
DS1123L
3.3V, 8-Bit, Programmable Timing Element
10 _____________________________________________________________________
To read the current values stored by the 3-wire
device(s), the latch must be enabled and the value of Q
must be read and then written back to D before the
register is clocked. This causes the current value of the
register to be written back into the DS1123L as it is
being read. This can be accomplished in a couple of
different ways. If the microprocessor has an I/O pin that
is high impedance when set as an input, a feedback
resistor (generally between 1kΩ and 10kΩ) can be
used to write the data on Q back to D as the value is
read (see Figure 5a). If the microprocessor has an
internal pullup on its I/O pins, or only offers separate
input and output pins, the value in the register can still
be read. The circuit shown in Figure 5b allows the Q
values to read by the microprocessor, which must write
the Q value to D before it can clock the bus to read the
next bit. If the Q values are read without writing them to
D (with the pullup or otherwise), the read is destructive.
A destructive read cycle likely results in an undesirable
change in the delay setting.
Figure 5c shows how to cascade multiple DS1123L’s
onto the same 3-wire bus. One important detail of writ-
ing software for cascaded 3-wire devices is that all the
devices on the bus must be written to or read from dur-
ing each read or write cycle. Attempting to write to only
the first device (U1) would cause the data stored in U1
MICROPROCESSOR
OUTPUT
OUTPUT
I/O PIN
LE
CLK
DQ
R
FB
MICROPROCESSOR
OUTPUT
OUTPUT
OUTPUT
INPUT
A) USING A FEEDBACK RESISTOR WITH AN I/O PIN FOR READING
THE DS1123L
B) USING A SEPARATE INPUT PIN TO READ THE DS1123L
MICROPROCESSOR
LE
CLK
DQ
LE
CLK
DQ
LE
CLK
DQ
OUTPUT
OUTPUT
I/O PIN
R
FB
C) CASCADING MULTIPLE DS1123L'S ON A 3-WIRE BUS
V
CC
V
CC
V
CC
V
CC
V
CC
LE
CLK
DQ
P/S P/S
P/S P/S P/S
DS1123L
DS1123L
U1 U2
U3
DS1123L DS1123L
DS1123L
Figure 5. Using the Serial Interface
DS1123L
3.3V, 8-Bit, Programmable Timing Element
____________________________________________________________________ 11
to be shifted to U2, U2’s data would be shifted to U3, etc.
As shown, the microprocessor would have to shift 24 bits
during each read or write cycle to avoid inadvertently
changing the settings in any of the 3-wire devices. Also
note that the feedback resistor or a separate input (not
shown) can still be used to read the 3-wire device set-
tings when multiple devices are cascaded.
Configuring the DS1123L as a Delay Line
To use the DS1123L as a delay line, the MS pin must
be tied to ground. When used as a delay line, the inter-
nal architecture of the DS1123L allows the output delay
time to be considerably longer than the input pulse
width (see AC specifications). This feature is useful in
many applications, in particular in clock phase control,
where delays up to and beyond one full clock period
can be achieved. Table 1 lists some of the delay char-
acteristics of the different speed options available for
the DS1123L device.
Using the Reference Delay
All delay lines have an inherent step-zero delay
between IN and OUT (t
D0
) due to the propagation
delay through the input and output buffers. To simplify
system design, a reference delay has been included on
the DS1123L that can be used to compensate for the
step-zero delay. The reference output allows the
DS1123L to be used to generate small differential
delays that cannot be generated when the OUT delay
is referenced to the input. The step-zero OUT delay is
always approximately 1ns faster than the REF delay
(see Figure 8). This allows the DS1123L to generate a
nondelayed output with respect to the reference output.
In addition, the reference output driver is sized similarly
to the OUT output driver, both outputs act similarly over
temperature, and they are both triggered at the same
time regardless of the exact input threshold. These fea-
tures make the output delay with respect to the refer-
ence act more ideally because both of these outputs
are skewed approximately the same amount due to
these phenomena.
Integral Nonlinearity
Integral nonlinearity (INL) is defined as the deviation from
a straight line response drawn between the measured
step-zero delay and the measured step 255 delay with
respect to the reference output. INL measured with
respect to IN is not specified, but should be slightly high-
er than when measured with respect to the reference out-
put. This is because measurements taken with respect to
t
EW
t
CW
t
ES
t
EH
t
DSC
t
EGV
t
CQX
t
CQV
t
EDZ
t
EQZ
t
EDX
t
DHC
t
CW
PREVIOUS VALUE
NEW
VALUE
NEW
BIT 7
NEW
BIT 0
NEW BIT 6
OLD BIT 7 OLD BIT 6 OLD BIT 0
ENABLE
(LE)
CLOCK
(CLK)
SERIAL
INPUT
(D)
SERIAL
INPUT
(Q)
DELAY
TIME
Figure 6. Serial Interface Timing Diagram
DS1123L
3.3V, 8-Bit, Programmable Timing Element
12 _____________________________________________________________________
IN do not benefit from the REF output’s tendency to track
OUT over temperature and voltage. Figure 9 shows INL’s
effect on delay performance graphically.
Configuring the DS1123L as a Monostable
Vibrator or PWM
To configure the DS1123L as a monostable vibrator, set
MS = 1. This causes the reference output (PWM) to be
set high between t
REF
and t
D
when it is triggered by the
input. After time period t
D
has elapsed, the output
returns low, and the monostable vibrator can be retrig-
gered. See Figure 10 for the timing of the OUT and
PWM signals. When MS = 1 and the DS1123L is trig-
gered by an external free-running oscillator, reference
output becomes a pulse-width modulator (PWM). When
using the DS1123L as a PWM, the free-running oscillator
should not be generated by connecting OUT to the input.
This causes the PWM period to change in addition to the
duty cycle as different values are programmed, which is
most likely not the desired functionality.
The minimum pulse width that can be practically gener-
ated is approximately 5ns. This is because a 5ns pulse
is approximately the shortest pulse that can be pro-
duced with the DS1123L’s output driver. The mono-
stable vibrator cannot be retriggered, so subsequent
triggering pulses into IN should not be present until
after the output has returned low.
Configuring the DS1123L as an Oscillator
To configure the DS1123L as an adjustable oscillator,
set MS = 1 and externally connect OUT to IN. Setting
MS = 1 by itself inverts the input signal in addition to
delaying it (see Figure 10). Connecting OUT to the
input then causes the circuit to oscillate with the period
being twice the programmed delay. Table 2 shows the
oscillator frequency ranges that the different speed
grades of DS1123Ls provide.
REF
IN
OUT
REF
IN
OUT
DS1123L
t
WI
t
REF
t
D0
t
DMAX
t
DMAX
Figure 7. Reference Delay Timing, MS = 0
DELAY
t
DMAX
t
REF
t
REF0
t
DREF
STEP
2550
t
D0
Figure 8. Delay Parameters
STEP
LINE FIT BETWEEN
MEASURED MAX
AND MIN DELAY
MEASURED DELAY
FOR ALL STEPS
0 64 128 192 255
INL
EXAGGERATED
DELAY
MEASURED
t
DREF
MEASURED
t
D0
t
REF
Figure 9. Integral Nonlinearity
P1-P3P4-P6P7-P9P10-P12P13-P14

DS1123LE-25+

Mfr. #:
Buy DS1123LE-25+
Manufacturer:
Maxim Integrated
Description:
IC DEL LN 256TAP 63.75NS 16TSSOP
Lifecycle:
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