Figure 1. Effective Differential Input Resistance/Offset Current
ELECTRICAL CHARACTERISTICS (PWM Controller) (continued)
(All voltages referenced to V-. V
DD
= 13V, a 10µF capacitor connects V
CC
to V-, V
CS
= V-, V+ = 48V, 0.1µF capacitor connected to
SS_SHDN, NDRV = open circuit, V
FB
= 3V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
Note 1: All min/max limits for the PD interface are production tested at +85°C (extended grade)/+70°C (commercial grade). Limits
at +25°C and -40°C are guaranteed by design. All PWM controller min/max limits are 100% production tested at +25°C
and +85°C (extended grade)/+70°C (commercial grade). Limits at -40°C are guaranteed by design, unless otherwise
noted.
Note 2: The input offset current is illustrated in Figure 1.
Note 3: Effective differential input resistance is defined as the differential resistance between GND and V
EE
without any external
resistance.
Note 4: Classification current is turned off whenever the IC is in power mode.
Note 5: See Table 2 in the PD Classification Mode section. R
DISC
and R
CL
must be 100ppm or better.
Note 6: See Thermal Dissipation section for details.
Note 7: When UVLO is connected to the midpoint of an external resistor-divider with a series resistance of 25.5kΩ (±1%), the turn-
on threshold set point for the power mode is defined by the external resistor-divider. Make sure the voltage on the UVLO
pin does not exceed its maximum rating of 8V when V
IN
is at the maximum voltage.
Note 8: When the V
UVLO
is below V
TH, G, UVLO,
the MAX5942_ sets the turn-on voltage threshold internally (V
UVLO,ON
).
Note 9: An input voltage or V
UVLO
glitch below their respective thresholds shorter than or equal to t
OFF_DLY
will not cause the
MAX5942A/MAX5942B to exit power-on mode (as long as the input voltage remains above an operable voltage level of 12V).
Note 10: PGOOD references to OUT while PGOOD references to V
EE
.
Note 11: Guaranteed by design.
