MAX8664
Low-Cost, Dual-Output, Step-Down
Controller with Fast Transient Response
22 ______________________________________________________________________________________
To set the no-load output voltage (V
OUT
), calculate the
value of R3 as follows:
where V
FB
is the feedback regulation voltage (0.6V
when using the internal reference or V
REFIN2
for exter-
nal reference). If the desired output voltage is equal to
the reference voltage (typical for tracking applications),
R3 is not installed.
To achieve the lowest possible load regulation in appli-
cations where voltage positioning is not desired, R1 is
not installed and R3 is calculated as follows:
Compensation
To ensure stable operation, connect a compensation
capacitor (Cr) across the upper feedback resistor as
shown in Figure 7. To find the value of this capacitor,
follow the compensation design procedure below.
Choose a closed-loop bandwidth (f
C
) that is less than
1/3 the switching frequency (f
S
). Calculate the output
double pole (f
O
) as follows:
The FB peak-to-peak voltage ripple is:
The output ripple voltage due to the ESR of the output
capacitor, C
OUT,
is:
Target the feedback ripple in the 25mV to 60mV range.
For high duty-cycle applications (> 70%), a feedback
ripple of 25mV is recommended.
Finally, calculate the value of Cr as follows:
MOSFET Selection
Each output of the MAX8664 is capable of driving two to
four external, logic-level, n-channel MOSFETs as the cir-
cuit switch elements. The key selection parameters are:
• On-resistance (R
DS(ON)
)—the lower, the better.
• Maximum Drain-to-Source Voltage (V
DSS
)—should
be at least 20% higher than the input supply rail at
the high-side MOSFET’s drain.
• Gate charges (Q
g
, Q
gd
, Q
gs
)— the lower, the better.
For a 5V input application, choose MOSFETs with rated
R
DS(ON)
at V
GS
≤ 4.5V. With higher input voltages, the
internal VL regulator provides 6.5V for gate drive in
order to minimize the on-resistance for a wide range of
MOSFETs.
For a good compromise between efficiency and cost,
choose the high-side MOSFETs that have conduction
losses equal to switching losses at nominal input voltage
and output current. Low R
DS(ON)
is preferred for low-
side MOSFETs. Make sure that the low-side MOSFET(s)
does not spuriously turn on due to dV/dt caused by the
high-side MOSFET(s) turning on, as this would result in
shoot-through current and degrade the efficiency.
MOSFETs with a lower Q
gd
/ Q
gs
ratio have higher
immunity to dV/dt. For high-current applications, it is
often preferable to parallel two MOSFETs rather than to
use a single large MOSFET.
For proper thermal management, the power dissipation
must be calculated at the desired maximum operating
junction temperature, maximum output current, and
worst-case input voltage. For the-low side MOSFET(s),
the worst-case power dissipation occurs at the highest
duty cycle (V
IN(MAX)
). The low-side MOSFET(s) operate
as zero voltage switches; therefore, major losses are
the channel conduction loss (P
LSCC
) and the body
diode conduction loss (P
LSDC
):
Use R
DS(ON)
at T
J(MAX)
:
P
LSDC(MAX)
= 2 x I
LOAD(MAX)
V
F
x t
DT
x f
S
where V
F
is the body diode forward-voltage drop, t
DT
is the
dead time between high-side and low-side switching tran-
sitions (25ns typical), and f
S
is the switching frequency.
